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Panometric
Level 5
Level 5
10 likes received 100 sign-ins 100 replies posted

Ever see and ADC input that changes if it's watched?

I have an ADC battery monitor that works as expected, ONLY IF you touch it ONE time after startup with anything, like a scope probe or even tweezers.  Unless you do this,  it reads a very high, impossible high value, as if the VSS is -3.3V. 

I realize there is a pin usage error that might cause this, and even though I will probably change it, I just want to understand why it works this way. The error is that Pin 5.1 is OVT tolerant, but P1.6 is not.  Even if P1.6 is left low it acts this way, so perhaps when the device is off, the pin protection is latching. 

If there is a software fix for this I would be interested in knowing, just because I despise ghosts in the machine. 

Thanks.  

 

bcf24a43-958e-4519-8ed7-b34280f5e442.png

 

int32_t MeasD=0;
int32_t retval=0;
VBAT_ADC_Start();
CyDelay(1);
VBAT_ADC_StartConvert();
VBAT_ADC_IsEndConversion(VBAT_ADC_WAIT_FOR_RESULT);
MeasD=(int32_t) VBAT_ADC_GetResult16(0); // Channel
VBAT_ADC_Stop();


Simplified SchematicSimplified Schematic

 

 

 

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1 Solution

@Panometric ,

I've spoken to an Infineon IC HW expert.

He confirms as long as the input current is limited to below the "latch-up" current both P5.1 and P1.6 show not be damaged or create a logical latch-up in the output even when P1.6 is driven low.

He did indicate that the OVT of P5.1 as a 5.5V max.   Exceeding 5.5V on P5.1 and/or exceeding 3.9V on P1.6 will probably forward-bias the body diode of the high-side output FETs on both of those pins.   

As @BiBi_1928986 indicated this could force about VBATT (6V) on the output of the Vreg (VR1).   It also can turn on internal circuits not intended to be on.   

I suspect that if VDDS is also near VBAT, your VDDA use as Vref for the ADC will be thrown off.

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

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8 Replies
PandaS
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 5 likes given

Hi @Panometric ,

Could you please share a screenshot of your VBAT_ADC and VBAT_MON GPIO Configuration. The VREF is set to?

Thanks and regards,

Sobhit

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VrefSel.pngChan.png

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

@Panometric ,

How is P1.6 (VBATMONEN) configured?

The latching you speak of on P1.6 is usually permanent and destructive.  Therefore, I don't think latching is the issue.

The latch up current required to damage P1.6 is 200mA.   With VBAT=6.6V and VDD=3.3V  and a total Rs to P1.6 of 142.2K ohms, you are looking at most 23.2uA.   

As long as you drive the low FET on, this should GND the VBATMONEN pin.  This would bring the maximum P5.1 input to (6.6V * 42.2K/142.2K 😃 1.96V.

Len
"Engineering is an Art. The Art of Compromise."
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Thanks for your replay Len. It's low by config, and I also set it at initialization.  I have the board on power monitor, so there is no high current. There is ~25uA when Off I have not been able to isolate, I believe 10 of it is the OVT pin. 

Vbatmonen.png

OVT Leak.png

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@Panometric ,

I've spoken to an Infineon IC HW expert.

He confirms as long as the input current is limited to below the "latch-up" current both P5.1 and P1.6 show not be damaged or create a logical latch-up in the output even when P1.6 is driven low.

He did indicate that the OVT of P5.1 as a 5.5V max.   Exceeding 5.5V on P5.1 and/or exceeding 3.9V on P1.6 will probably forward-bias the body diode of the high-side output FETs on both of those pins.   

As @BiBi_1928986 indicated this could force about VBATT (6V) on the output of the Vreg (VR1).   It also can turn on internal circuits not intended to be on.   

I suspect that if VDDS is also near VBAT, your VDDA use as Vref for the ADC will be thrown off.

Len
"Engineering is an Art. The Art of Compromise."
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@Len_CONSULTRON Thanks for following up. It does seem like the high side output of P1.6 is conducting, but it does not send Vdd to 6V, it sends it to 0.6V when the device is off. So somethings else is also conducting. Perhaps it's just too complex to understand without being able to measure inside. 

BTW: I can't find 5.5V OVT limit in the datasheet, but it does seem it should be mentioned. Nevertheless, I've clearly made an error exposing this part to over voltage when the device is off.  It's also a leakage path that will kill my battery when in storage. 
I'll remedy that with this circuit using a DMC2400UV and be more careful next time. 

V Battery Mon.png



 

BiBi_1928986
Level 7
Level 7
First comment on blog 500 replies posted 250 replies posted

Hello.

You gave a good hint in your description...,  "as if the VSS is -3.3V".
If you measure the output of VR1 in this weird condition, you'll likely see close to 6V.  That's because it's VR1 that's latched up (hence it doesn't regulate).

You are correct, there is a sneak current flowing up thru P1.6 protection diode towards Vdd inside the chip.  This is then presented to the output of VR1, which causes VR1 to latch up.

One solution is to place a diode across VR1 with diode cathode at VR1 input and diode anode at VR1 output.  I'd suggest a low voltage drop diode like 1N5819.

However, since schematic does not show a mechanism to remove battery voltage, I don't understand how "when the device is off" enters into the picture.  (The diode I mentioned above only works when input voltage is removed.)

Where in the circuit do you touch the circuit "once" to get it running?  Need details.

Don't assume Cypress/Infineon has inter-connected all the grounds (or Vdd's for that matter).  Pin 25 of U2 should be tied to ground.

Have you tried connecting R9 to ground in place of P1.6 (P1.6 disconnected in this case)?  This would eliminate at least 1 sneak current path.

Is there another voltage source driving 3v3 that's not shown?

The code snip doesn't show any control of VBATMON_EN.  Has this been deleted?

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@BiBi_1928986 Thanks for your thoughts. The VR circuit has been simplified. There is a diode isolated and zener regulated manual,  and software drive the the VR Enable not pictured.  It is working as expected with 0V on enable when off.  Also all the GNDs are also tied. But I measured VR out in off and on state. It never exceeds 3.3,  but, it is 0.6V when OFF which does suggest you are onto something.  The Psoc is feeding the VBATMON back into VDD. 

Regarding the touching analog in VBATMON once, the first sample and every sample after any touch to an open circuit fixes the issue. That's what confuses me about this, the same node is driven by the divider. Why does it act like an open CMOS input circuit?

Per your suggestion,  I tied VBATMON_EN to GND this this drops VDD while off to 0.2V, and the ADC problem goes away, and as might be expected, the OFF current increases 10uA. 

So my solution is clearly not to use P1.6 the way I have. Intellectually I'm still confused why the analog in is sensitive to static when the input is driven to ~1.5V. 

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