Reset operation for CY8C4245PVI-482

[KaKi_1384211]

Hi Team,

Please let me know regarding reset operation of CY8C4245PVI-482.
1) Is the state of GPIO pin "Hi-Z" at reset?

2) Is the special procedure such as delay necessary for the reset pin sequence in the POR sequence at power-on?

Is it OK at the same time that power-on and reset cancellation are performed during control?

Or is there any need to delay anything?

3) We are considering adding the damping resistance(1K ohm) and the capacitor (0.01 uF), but are there restrictions on the above power-on and reset sequence timing?

4) I understand that "internal pull-up is effective", but is there any opinion that external pull-up is not necessary or not good?

The customer would like to confirm whether there is a problem with only the resistance in the device.

Thanks and regards,

[Anonymous · Accepted solution]

1) Pg 8 of TRM has the information you are looking for: http://www.cypress.com/file/138656/download  The pins are set to analog Hi-z on reset.

2) The power-on delays are implemented for the voltage-regulator to get the power voltage setup and for the CPU crystal/oscillator to stabilize. Whether you need to wait for these, or what you can do to shorten/skip them I don't know. Once your code from main is running, then the chip is fully ON/READY.

3) No idea. Datasheet/manual would be your best bet for this information.

4) External pull-ups will work well too, but with the presence of internal pull-ups, you are adding extra hardware and cost for an otherwise redundant function. The internal resistance is stated in the datasheet, and works well from what I've seen in testing. The internal pull-ups will work well for logic voltage levels (0-5 volts), but if you have the desire to more accurately regulate your pull-up resistance and electrical characteristics than by all means an external pull-up will work well too.

[Vasanth]

Hi,

2&3)POR circuit monitors VCCD  and provides a rese trigger on power ramp. In case of adding external circuitry, it is always advisable to follow the Hardware design guideline <http://www.cypress.com/documentation/application-notes/an88619-psoc-4-hardware-design-considerations>

Best Regards,
VSRS