Regarding external clock frequency of PSoC4100S(IMO is 24MHz).

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YuMa_1534086
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Hello.

 

When CY8C4126AZQ-S433(IMO is 24MHz) is used, is it possible to use a 48MHz external clock?

 

If external clock is set to 48MHz, an error will be displayed like a below figure.

YuMa_1534086_0-1626072382305.png

 

However, if divider is set to 2, an error disappears and build succeeds.

YuMa_1534086_1-1626072427606.png

 

Is it possible to use 48MHz external clock that exceeds the IMO's 24MHz by setting the divider to 2?

PSoC4100S datasheet explains that the upper limit of the external clock is 48MHz.

 

YuMa_1534086_2-1626072446032.png

 

I think that even 24MHz PSoC4100S can use 48MHz external clock by setting the divider to 2.

Because build was successful and datasheet also explains that upper limit is 48MHz.

 

However, I would like to confirm that the understanding is correct just in case.

 

 

Best Regards.

Yutaka Matsubara

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MotooTanaka
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Hi,

The upper limit of the external clock of datasheet is 48MHz.

So the device is accepting 48MHz as the External Clock,

but since the CPU can not accept more than 24MHz,

the clock divider requires to have "div 2".

So even when SysClk is 24MHz, the device is receiving 48MHz as the external clock,

which I hope is not inconsistent with the statement of Datasheet.

moto

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MotooTanaka
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Hi,

Reading the Ordering Information in the datasheet

Max CPU Speed of 412x is 24MHz, 414x is 48Mhz.

I'm afraid that this was the reason.

Ordering_info.JPG

moto

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YuMa_1534086
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Hi.

 

I'm asking about external clocks, not IMOs.

 

The upper limit of the external clock of datasheet is 48MHz.

 

Best Regards.

Yutaka Matsubara

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MotooTanaka
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Hi,

The upper limit of the external clock of datasheet is 48MHz.

So the device is accepting 48MHz as the External Clock,

but since the CPU can not accept more than 24MHz,

the clock divider requires to have "div 2".

So even when SysClk is 24MHz, the device is receiving 48MHz as the external clock,

which I hope is not inconsistent with the statement of Datasheet.

moto

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YuMa_1534086
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Hi.

 

Thank you for your response.

 

I asked this question just in case to obtain opinion from Infineon.

I did not think it's a problem(so external 48MHz is OK), but I created this thread for confirmation just to make sure.

 

Is it okay to think that your answer is the same as the answer from Infineon?

 

Best Regards.

Yutaka Matsubara

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Ekta
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Hi @YuMa_1534086 ,

Its OK to use an external clock of 48 MHz when the HFCLK divider is set to 2 as the Maximum CPU speed for the part is 24MHz. 

Best Regards

Ekta

MotooTanaka
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Hi,

I think that the followings are true (from the datasheet)

(1) The max CPU speed of CY8C4126AZQ-S433 is 24MHz

Datasheet > Ordering Information

(2) The max External Clock frequency of CY8C4126AZQ-S433 is 48MHz

Datasheet > Table 36. External Clock Specifications

So I think that this is not "My Opinion" but the statement from Cypress (now Infineon?)

But meantime, I don't mind if you need to wait for the answer from Cypress 😉

moto

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YuMa_1534086
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Hi moto-san.

 

Thank you for your response.

 

I understand.

 

Best Regards.

Yutaka Matsubara

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