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## Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Hello.

I measured RawCount, IDAC and CP at each resolution setting by using CY8CKIT-145-40XX.

Attached excel file is test result and attached zip file is test FW.

Q1)

I calculated Cs value by using equation 3-6 of capsense design guide(001-85951).

Cp value(resolution is 12 to 16bit) became about 3pF.

Cp value(resolution is 7 to 11bit) became about 12pF.

Please confirm “Used Equ” cell of excel file.

“Used API” cell value is Cp value acquired by using API(CapSense_GetSensorCapacitance ).

This value is 12 pF in resolution range from 6bit to 12bit.

Why does Cp value change significantly when resolution is 12bit? (12pF => 3pF)

And why does modulator IDAC change significantly when resolution is 12bit? (25 => 6)

Which value is correct? 3pF? 12pF?

Q2)

When resolution is made smaller, RawCount tends to saturate.

In this case, RawCount is saturated when resolution is 6bit.(RawCount is 52).

Why does RawCount saturate if resolution setting is low(for example, resolution is 6bit)?

Modulation IDAC at 7bit is 23.

IDAC can still be increased since max modulation IDAC value is 250.

Nevertheless, RawCount is saturated at 6bit.

And IDAC was largely changed from 23 to 1.

Why is RawCount saturated at 6bit?

Why is IDAC changed significantly at from 7bit to 6bit?

Could you please let us know mechanism and theory that RawCount became saturation?

Best Regards.

Yutaka Matsubara

1 Solution

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hi YuMa_1534086

1. Regarding calculation of Cp value using equation, please set the clock source to "Direct" for measurement. You will observe 24 as IDAC code and the capacitance will be 12 pF for 16 to 12 bits resolution as well.

2. For 6 bit resolution, the sense clock frequency is very low. Please increase the sense clock frequency to 3000 kHz or 6000 kHz and verify the value.

In both the cases, it can be observed that the IDAC code is very small. It is recommended to keep IDAC code greater than 18 for better sensitivity and performance. All other parameters have to be tuned in order to maintain IDAC code greater than 18. Since Vref and Cs are fixed, the parameter that has to be tuned is Fsw, sense clock frequency.

Also, it is recommended to use the new component, CapSense V6.0 for the latest IP and enhanced features. You can update the component by clicking Project -> Update components.

Thanks and regards
Harigovind

10 Replies

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hi YuMa_1534086

1. Regarding calculation of Cp value using equation, please set the clock source to "Direct" for measurement. You will observe 24 as IDAC code and the capacitance will be 12 pF for 16 to 12 bits resolution as well.

2. For 6 bit resolution, the sense clock frequency is very low. Please increase the sense clock frequency to 3000 kHz or 6000 kHz and verify the value.

In both the cases, it can be observed that the IDAC code is very small. It is recommended to keep IDAC code greater than 18 for better sensitivity and performance. All other parameters have to be tuned in order to maintain IDAC code greater than 18. Since Vref and Cs are fixed, the parameter that has to be tuned is Fsw, sense clock frequency.

Also, it is recommended to use the new component, CapSense V6.0 for the latest IP and enhanced features. You can update the component by clicking Project -> Update components.

Thanks and regards
Harigovind

Attachments are accessible only for community members.

## Re: Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Harigovind-san.

I measured each data by changing parameter setting.

Attached file is test data.

Q1)

If sense clock source changes from “Auto” to “Direct”, Cp value using equation matched value obtained by API.

Please confirm “Direct” sheet of attached file.

When sense clock source is “Auto”, why does Cp value not match?

And why does Cp value match in the range from 7bit to 11bit even if sense clock source is “Auto”?

When sense clock source is “Auto”, why is there point where IDAC change greatly depending on resolution setting?

Is equation 3-6 of capsense design guide(001-85951) not an accurate formula?

Does formula change depending on setting of sense clock source?

.

Q2)

When sense clock freq is 6000kHz, raw does not become saturation.

Please confirm “6000kHz” sheet of attached file.

Why is raw saturation at low resolution solved by using higher sense clock freq?

Why is high frequency needed when using low resolution?

Best Regards.

Yutaka Matsubara

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hello

1. For calculating Cp, the sense clock must be direct. If it is configured to PRS or SSC, the sense clock itself will be variable and spread out, therefore, the sense clock parameter in the equation is not valid.

When you set the sense clock source to "Auto", the algorithm gives priority to SSC, PRS and finally Direct.

For SSC, the following conditions must be satisfied

For PRS, the following equations must be satisfied

where N is the resolution and PRSN is the number of bits used for PRS (8 or 12)

If you calculate the resolution for PRS 8, the resolution must be greater than or equal to 12.

(2^x - 1)/24 >= (2^8 - 1)/1.5  => x >= 12

Therefore, when the resolution was greater than or equal to 12, the clock source chosen by the component was "PRS8". Since condition for PRS8 was not satisfied for resolution lower than 12, the clock source chosen by component was "Direct". Hence, the calculation was correct for 7 to 11 bits resolution since clock source was direct.

2. The Imod auto calibration is limited by the auto calibration feature of the component. This is a limitation by the component. The Imod value calculated was really small for the parameters that the lowest value of 1 was chosen. Increasing the sense clock frequency resulted in increase of Imod for the same percentage of raw counts and hence, the sensitivity was better.

In general, it is recommended to make sure that Imod is greater than 18.

Thanks and regards
Harigovind

## Re: Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Dear Harigovind-san.

>>In general, it is recommended to make sure that Imod is greater than 18.

Best Regards.

Yutaka Matsubara

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hello Yutaka Matsubara san

This is not explained in any documented. In general, when IDAC is lower than 18, the noise in the system is increased as raw counts is inversely proportional to Imod. Wen Imod is low, a small change in Cp will lead to large change in raw counts.

Hence, we recommend not lowering IDAC code below 18.

Thanks and regards
Harigovind

## Re: Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Dear Harigovind-san.

Q1)

When do you document about recommended IDAC range?

Do you have any plans to add recommended IDAC range into any documents?

There is no way for users to consider content that is not listed anywhere.

Even if an instruction is received that it is necessary to change the setting because IDAC is lower than recommended range just before the evaluation is completed, it may be difficult that user change setting from there.

Because evaluation needs to do all over again from the beginning if setting changes.

Q2)

If SNR is 5 or more, is it OK even if modulator IDAC is lower than 18?

Q3)

Could you please let us know each recommended range both modulator IDAC and compensation IDAC when compensation IDAC enabled?

Q4)

A) Increasing the sense clock frequency resulted in increase of Imod for the same percentage of raw counts and hence, the sensitivity was better.

B) Wen Imod is low, a small change in Cp will lead to large change in raw counts.

A) explains that increasing Imod increases sensitivity.

On the other hand, B) explains that sensitivity increases if Imod decreases.

Q5)

In “Auto” tab of “P4S_ResoRawCp_02.xlsx”, why did IDAC change from 23 to 1 when resolution changed from 7bit to 6bit?

==================

7bit:       IDAC is 23.

6bit:       IDAC is 1

==================

Below red square is fix value.

Because Vref, Fsw and Cs are fix value.

And Calibration target is 85%.

So below red square should be fixed at 0.85.

So IDAC value will not change unless calibration target and sense clock source change.

Could you please let us know a reason why IDAC value changed although calibration target and sense clock source did not change?

(sense clock source of 7bit and 6bit is Direct)

Best Regards

Yutaka Matsubara

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hello YuMa_1534086

1. We have notified our internal team and we will be adding this to our documents.

2. In general, it is recommended to keep IDAC value greater than 18.

3. This is dependent on the board that is being used. The constraint is on Mod Idac value. Keeping this at 18, find the compensation IDAC value that sets the raw counts to 85%. You can also use smartsense for reference values. Note down the values obtained using smartsense and then tune for better performance.

4. Yes. Apologies for the confusion. When Imod is low, the sensitivity is high and the noise observed will also be very high. When the Imod value is greater than 18, the signal level will be improved as noise in the system is lowered.

5. This is a limitation of the auto calibration feature of the component. The Imod value calculated was really small for the parameters that the lowest value of 1 was chosen. Increasing the sense clock frequency resulted in increase of Imod for the same percentage of raw counts. Modulator clock frequency used is 24 MHz and the resolution set is 6. Hence, the total scan time is 2.6 us. In 2.6 us, only 4 cycles of sense clock will be performed ( (2^6 - 1)/24000000)*1500000. This is not sufficient to calibrate IDAC value and therefore, it was causing an error in calibration. But if you set the IDAC value manually to 24 (thereby maintaining the ratio to 0.85), you will observe that the sensor works and the calculation is correct.

Do let us know in case of any further queries.

Thanks and regards

Harigovind

## Re: Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Dear Harigovind-san.

Sorry, I have some questions.

Q1)

Could you please let us know a number of sense clock cycles required to complete calibration wihtout error?

Which document describes required number of sense clock cycles?

Q2)

If autocalibration is enabled and scan resolution is 6bit, IDAC became 1 and RawCount became saturation.

The cause of saturation is not Cp, but calibration error by insufficient sense clock cycles caused RawCount saturation.

Because this RawCount saturation is solved if autocalibration is disabled and IDAC value sets 24.

Is my understanding correct?

Q3)

Is there a way to check if there is calibration failure like this case(insufficient sense clock cycles) or not?

Is there sample code for it?

Is calibration failure by insufficient sense clock cycles determined as “Calibration Failure” inside the IC?

Or since RawCount itself is within +/- 10% of calibration target, is this symptom judged as “Calibration Success” as IC internal process even though RawCount is saturated?

Best Regards.

Yutaka Matsubara

## Re: Regarding RawCount, IDAC and CP of Capsense.

Moderator
Moderator

Hello Yutaka Matsubara-san

1. SmartSense and Auto calibration are Cypress proprietary information and this is not shared with the public through any document.

2. Yes. This is the correct reason.

3. If the raw counts are not within +/-10%, then CapSense_Start will not return CYRET_SUCCESS and this can be checked to detect any errors. In this case however, the baseline is set to 52 (which is 81% of 2^6) and therefore, it is not returning the error status.

Thanks and regards
Harigovind

## Re: Regarding RawCount, IDAC and CP of Capsense.

Level 7
Level 7
Distributor - Macnica (Japan)

Dear Harigovind-san.