Regarding PSoC4000S POWER_MODE bits. / #NOF

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YuMa_1534086
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Hi infineon.

 

I have a question about registers TRM of PSoC4000S.

This document has a description of POWER_MODE of below figure.

https://www.infineon.com/dgdl/Infineon-PSoC_4000S_FAMILY_PSoC(R)_4_REGISTERS_TECHNICAL_REFERENCE_MAN...

 

YuMa_1534086_0-1706587984121.png

 

Is it possible for the user to read modes other than the CPU's active mode?

Since the CPU should be active when accessing the register to read POWER_MODE, I don't think it is possible to check whether it is in a mode other than active.

 

Best Regards.

YuMa

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Hi @YuMa_1534086 

Once the MCU moves to sleep or deep sleep mode, the access to read the registers(here the power register) will be restricted. Since the MCU will be in retention state. In sleep mode, the Cortex-M0 CPU enters Sleep mode and its clock is disabled. In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention. The high-frequency clocks, including HFCLK and SYSCLK, are disabled.

That is in both cases, since there is no clock source supply, the MCU is not active and cannot access the register for read. The TRM explains the different states but the entry to sleep and deep sleep modes are completely mediated by the MCU internally. The register content can only can only be read correctly after the MCU wakes up from any of the interrupts as shown below:

LeoMathews_0-1706618480619.png

Since the CPU is inactive it is not possible to read the PWR_CONTROL register showing the states during debugging. But you can utilize the shared code example to determine the current state of the MCU whether it is in sleep or deep sleep mode.

Thanks and Regards,
Leo

 

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LeoMathews
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First question asked 500 replies posted 100 solutions authored

HI @YuMa_1534086 

You are correct. The CPU should be active when accessing the register to read the POWER_MODE. So it is not possible to read the mode from the POWER_MODE register while debugging when the MCU enters sleep or deep sleep mode. The mode status remain active(previous state) when the execution jumps to the sleep or deep sleep function calls.

LeoMathews_0-1706595028122.png


You can refer to the code example PSoC4 power modes for knowing the current mode of operation. In this code example you can observe the power mode in an UART terminal by switching between the modes of operation. 

Thanks and Regards,
Leo 

 




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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Leo-san.

 

Thank you for your support.

 

Is there same code sample of PSoC Creator version?

 

Best Regards.

YuMa

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Hi @YuMa_1534086 

You can find a similar code example in PSoC Creator from here
https://www.infineon.com/dgdl/Infineon-Code_Examples_PC41-ApplicationNotes-v09_00-EN.zip?fileId=8ac7...

Thanks and Regards,
Leo

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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Leo-san.

 

Sorry, I have additional questions.

 

POWER_MODE bits cannot be read externally, but do these bits change internally when sleep mode or deep sleep mode?

Do POWER_MODE bits change to 0x2(Sleep) or 0x3(Deep Sleep) internally from 0x1(Active)?

 

Is there any reason why TRM explains about sleep state or deep sleep state of POWER_MODE that cannot be read by user?

 

Best Regards.

YuMa

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Hi @YuMa_1534086 

Once the MCU moves to sleep or deep sleep mode, the access to read the registers(here the power register) will be restricted. Since the MCU will be in retention state. In sleep mode, the Cortex-M0 CPU enters Sleep mode and its clock is disabled. In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention. The high-frequency clocks, including HFCLK and SYSCLK, are disabled.

That is in both cases, since there is no clock source supply, the MCU is not active and cannot access the register for read. The TRM explains the different states but the entry to sleep and deep sleep modes are completely mediated by the MCU internally. The register content can only can only be read correctly after the MCU wakes up from any of the interrupts as shown below:

LeoMathews_0-1706618480619.png

Since the CPU is inactive it is not possible to read the PWR_CONTROL register showing the states during debugging. But you can utilize the shared code example to determine the current state of the MCU whether it is in sleep or deep sleep mode.

Thanks and Regards,
Leo

 

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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Leo-san.

 

>>> But you can utilize the shared code example to determine the current state of the MCU whether it is in sleep or deep sleep mode.

Is my understanding correct that this code uses UART to inform the external of next CPU mode before entering sleep mode or deep sleep mode?

 

Best Regards.

YuMa

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LeoMathews
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First question asked 500 replies posted 100 solutions authored

Hi @YuMa_1534086 

Yes, the shared code uses UART to inform the next CPU mode before entering sleep or deep sleep mode. The MCU wakes up after it encounters an external interrupt.

Thanks and Regards,
Leo

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YuMa_1534086
Level 7
Level 7
Distributor - Macnica (Japan)
500 replies posted 250 sign-ins 10 likes received

Leo-san.

 

Thank you for your support.

I understand.

 

Best Regards.

YuMa

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LeoMathews
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First question asked 500 replies posted 100 solutions authored

Hi @YuMa_1534086 ,

Thread was locked due to inactivity for long time, you can continue the discussion on the topic by opening a new thread with reference to the locked one. The continuous discussion in an inactive thread may mostly be unattended by community users.

Thanks and Regards,
Leo

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