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I’ve found:
- I2C FM+ mode is NOT supported in PSoC 4100S due to lack of OVT-GPIO pins.
- I2C speed appears to be limited to 50KHz due to lack of PLLs
- Using ISRs appears to have an affect on the maximum I2C speed.
Are there other features within PSoC components that either enable or limit the maximum speed for I2C communication?
I’m specifically having issues attempting to implement an I2C slave in a CY8C4125AZI-S433 at any speed over 50kHZ.
The design worked without issue in a PSoC 4200M (using CY8CKIT-044).
The PSoC 4S parts do NOT contain PLLs, which appears to limit the accuracy of internal clocks, thus limiting higher I2C speeds. Reference: Knowledge Based Article clarifying the difference between PSoC 4S and 4S Plus @ https://community.cypress.com/docs/DOC-14404
All comments appreciated.
Greg
Solved! Go to Solution.
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Hi GrCa_1363456,
PSoC 4100S device supports up to 1 Mpbs data rate as per datasheet. The issue could be due to timing issues in the I2C bus. Could you please recheck the pull up resistors value used in accordance to the pull up resistor sizing mentioned in the @https://www.nxp.com/docs/en/user-guide/UM10204.pdf .
Rp max = tr /(0.8473 x Cb )
Where tr -> is the Rise time defines in the I2C spec as per speed
Cb is the total bus capacitance.
If this doesn't solve your issue, please share the I2C waveform.
Regards,
Bragadeesh
Bragadeesh
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Hi GrCa_1363456,
PSoC 4100S device supports up to 1 Mpbs data rate as per datasheet. The issue could be due to timing issues in the I2C bus. Could you please recheck the pull up resistors value used in accordance to the pull up resistor sizing mentioned in the @https://www.nxp.com/docs/en/user-guide/UM10204.pdf .
Rp max = tr /(0.8473 x Cb )
Where tr -> is the Rise time defines in the I2C spec as per speed
Cb is the total bus capacitance.
If this doesn't solve your issue, please share the I2C waveform.
Regards,
Bragadeesh
Bragadeesh