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PSoC™ 4

XiaoPing_Yang
Level 4
25 replies posted 10 replies posted 10 questions asked
Level 4

Hi sir,

     My custom use CY8C4014SXI-421 , he asks if he tied unused pin to GND ,is there much risk to damage the chip ?

     And how to configure it  ,when tied to GND .

     Thanks.

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BiBi_1928986
Level 7
250 replies posted 250 sign-ins 100 solutions authored
Level 7

Hello.

For this device package, the device FLASH programming pins (SWD_CL P3.1, SWD_IO P3.0 ,XRES P1.6) can also be used as GPIO.

DO NOT connect P1.6 (XRES) to GROUND.  If you do, the device will not come out of internal reset state.

P1.6 (on this device) should be used as an output.  If it is used as an input, your hardware must guarantee this pin is logic 1 or high impedance during power up.

I agree with RoyL for all other unused GPIO pins.

Bill

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Roy_Liu
Moderator
Moderator 500 solutions authored 5 questions asked First question asked
Moderator

By default, IO pins are come out as Hi-Z state after power on, need not configure unused IOs whether tied them to GND or not (floating).

If the IO is assured not used, there should be no risk. There is a chance that the PSoC Creator can use the unused pin switches for routing the analog signals, if so, the IO should be left floating.

For better EFT immunity performance, the unused I/O lines should be terminated to ground or supply through resistors of typical value of 10K Ohm.

Roy Liu
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XiaoPing_Yang
Level 4
25 replies posted 10 replies posted 10 questions asked
Level 4

Thanks.

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BiBi_1928986
Level 7
250 replies posted 250 sign-ins 100 solutions authored
Level 7

Hello.

For this device package, the device FLASH programming pins (SWD_CL P3.1, SWD_IO P3.0 ,XRES P1.6) can also be used as GPIO.

DO NOT connect P1.6 (XRES) to GROUND.  If you do, the device will not come out of internal reset state.

P1.6 (on this device) should be used as an output.  If it is used as an input, your hardware must guarantee this pin is logic 1 or high impedance during power up.

I agree with RoyL for all other unused GPIO pins.

Bill

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XiaoPing_Yang
Level 4
25 replies posted 10 replies posted 10 questions asked
Level 4

Hi Bill,

     Thanks.

     But P1.6 is not discribed as XRES  in its datasheet. Its a 16 pin SOIC chip.

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BiBi_1928986
Level 7
250 replies posted 250 sign-ins 100 solutions authored
Level 7

Hello.

In device datasheet pinout table, look to rightmost column for P1.6 "alternate" description for SO16 package.  It mentions this pin is Internal Reset function.  Also, read Note #1.  "Must not have load to ground during POR (should be an output)."

In the Programming Specification document: 002-22325_CY8C4xxx_CYBLxxxx_Programming_Specifications
"If the XRES pin is not available on the part’s package, the Power Cycle mode is the only way to reset a part."

I agree with you, the datasheet does not explicitly call this alternate function XRES.  However, it performs the same function of resetting the device internally during power-up.  This is also shown in Architecture TRM manual under "Power Mode Transitions State Diagram".

regards,
              Bill

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XiaoPing_Yang
Level 4
25 replies posted 10 replies posted 10 questions asked
Level 4

Hi Bill,

     I doubt that if P1.6 colud be configured as a touch pin. Is there any details to avoid problems?

     Thanks.

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Roy_Liu
Moderator
Moderator 500 solutions authored 5 questions asked First question asked
Moderator

P1.6 can be configured as touch pin. The KBA below should be able to help you.

I/O System Restrictions in the PSoC® 4000 Family – KBA91258

Roy Liu
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BiBi_1928986
Level 7
250 replies posted 250 sign-ins 100 solutions authored
Level 7

RoyL has provided KBA91258 with necessary details.  Thank you RoyL.

Bill

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