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PSoC™ 4 Forum Discussions

lschmid
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We use the cypress chip as controller of a battery management systems (BMS). Sporadic we have seen that chips misbehave. We've been unable to bring the chip in the misbehave state intentionally but discovered many occurrences over last year many BMS devices.What is the misbehaviour:- the cypress chip suddenly starts to consuming much higher power and heats up (>70°C).- Software reset, reset over XRES or flashing different software doesn't help to get out of this high power consumption state.- Only a full power off cycle might bring the chip back to normal power consumption. (Some keep consuming more).My feeling is that the misbehaviour gets triggered by going in/out of DeepSleep, hibernate or similar but as already mentioned we were not able to trigger it on purpose. While going into the sleep state all unnecessary devices were turned off and the power source is switched to a LDO (3.3V), while active run a DC_DC converter with 3.5V is used. The VDDA and VDDD stays active but VRef is switched off.What have we done to debug that:- We verified the supply voltages- Flashed a example when the chip was in this state (SysTick_Example with adapting/using the minimal GPIO to shown on our board).
- Tried to reset over Softreset, XRES
- using different capacitors/filters on VccD and VDDA/VDDD
Have you ever heard of a problem like this? Do you have an idea what the reason could be, how it could be provoke or most important how we could prevent getting into this mode?Looking forward for your feedback

 

 

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Vasanth
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Hi Lukas,

Kindly check the suggestions from Len for a PSoC5 device, 

https://community.infineon.com/t5/PSoC-5-3-1/PSoC-5LP-latent-shorts/m-p/200871#M35086

This could help you eliminate some of the not-so-obvious issues too.

Best Regards,
Vasanth

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Vasanth
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Hi,

The first thing I could request you to check is to confirm all the suggestions in the Hardware Design Guide are met. Additionally as you have doubt on the transition to low power states, kindly let us know how you are doing the transition. Check this appnote for reference too. We are checking internally if we have seen any similar issues, but if we are able reproduce it( with exact steps) that would have been really helpful. Meanwhile we ll go through the attached schematic segements.

Best Regards,
Vasanth

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lschmid
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Hi Vasanth,

Thanks a lot for your response.

I rechecked the Hardware Design Guide. I verified that

  • all the pins have the corresponding capacitors. Additional there is an inductor in the power line before VDDD and VDDA. I assume this is not causing any problem.
  • VDDA is always higher or equal than VDDD. They are on the same power. Additional VDDD has more capacity on there pins which should cause the voltage ramp up a bit slower.
  • Power ramp-up: I haven't found any specifications of the power on ramp of our LDO. But since the problem appearers a long time after the PSOC has been started, I hope this is not so relevant.
  • The PSoC creator settings are all on 3.3V (except the VBUS which is 5V). VBUS (pin 25/p13.2) but alsoPort13  (pin 23&24, P13.0&P13.1) are not connected.
  • Clocks correctly configured. Only WCO set to 32.768kHz with 5ppm.
  • From what I checked no GPIO is consuming more than 4mA.
  • XRES has no capacitor. Do you think that is the problem? But I haven't seen resets on this devices before they went into this state.

Then about the reproducible. That is exactly the same issue we have as well. We can't trigger it on purpose. We even tried to have a disconnected VDDA, different/no capacitors, no induction at VDDD/VDDA.

As said before, this problem occurs not always and sometimes after a running multiple months. If you have any good idea what we could try to trigger it I m happy to test.

Below I have our sleep and hibernate function calls:

void sleep_until_event()
{
//    Timer_1_Sleep();
    Timer_2_Sleep();
    UART_1_Sleep();
    CURRENT_TIMER_Sleep();
    
    // switch power states
    NC_EN_Write(1);         // Turn off Non-Critical components
    DC_DC_EN_Write(0);      // disable DC2DC --> move to LDO
    
    // Sleep
    CySysPmDeepSleep();
    
    // after wake
    DC_DC_EN_Write(1);      // enable DC2DC
    NC_EN_Write(0);         // Turn on Non-Critical components
    
//    Timer_1_Wakeup();
    Timer_2_Wakeup();
    UART_1_Wakeup();
    CURRENT_TIMER_Wakeup();
}
void enter_hibernate_mode()
{
    NC_EN_Write(1);      // Turn off Non-Critical components
    DC_DC_EN_Write(0);      // disable DC2DC --> move to LDO
    MAINS_EN_Write(0);      // disable MAINS output
    CySysPmHibernate();
    printf("CySysPmHibernate() failed, calling CySoftwareReset()\r\n");
    CySoftwareReset();
}

 

Do you need any other infos/code?

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MadenoorKris
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Hi @lschmid ,

To understand the root cause of this behavior,  could you keep PSoC 4 always in active mode and keep a tab on the power consumption? If this happens in this condition also, then we get some direction to debug. We will do iterative tests to see where and what causes the power/temperature rise. 

Regards,

Ram

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Hi @MadenoorKris ,

That is what we will be doing (having a simple firmware which can trigger the different power states and measure the current in it).
I ll let you know about the result.

Best,

Lukas

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Vasanth
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250 sign-ins 500 solutions authored First question asked

Hi Lukas,

Kindly check the suggestions from Len for a PSoC5 device, 

https://community.infineon.com/t5/PSoC-5-3-1/PSoC-5LP-latent-shorts/m-p/200871#M35086

This could help you eliminate some of the not-so-obvious issues too.

Best Regards,
Vasanth

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Hi Vasanth,
Last week we ere actually able to identify and verify our problem.

The problem was, that we used a broken test adapter which had the UART ground disconnected. Because of that the RX/TX were floating.

Further we verified that if the UART TX is below -1.5V (which is out of spec), the PSOC4 gets in a weird power state on which it only recovers with a power reset.

Thanks a lot for helping us and keeping looking for possible solutions.

Best Regards,
Lukas

Vasanth
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Hi Lukas,

Happy to know that the issue is resolved at your end !

Happy Designing !

Best Regards,
Vasanth

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