Since with BLE PA module CYBLE-224110-00 is discontinued. I designed with CY8C4248 + PA(used same PA in CYBLE-224110-00).
But following PA LNA control code for CYBLE-224110-00 is not working.
/* define the test register to switch the PA/LNA hardware control pins */
#define CYREG_SRSS_TST_DDFT_CTRL 0x40030008
/* Configure the Link Layer to automatically switch PA control pin P3 and LNA control pin P3 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_RF_CONFIG), 0x0331);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_SRSS_TST_DDFT_CTRL), 0x80000302);
How should I modify these numbers? At least I need where these values come from, which document should I refer?
The BLE_BLESS_RF_CONFIG register is used to DDFT mux. By writing 0x0331, we are bringing out the tx and rx enable lines so that they can be routed to external pins.
If you want to turn off the PA, dont change any values in these registers, instead change the CPS and CSD values, i.e. CSD_Write(0) and CPS_Write(0).
This link might be helpful:
Is this number same as for CY8C4248 devices? Since this device is different silicon version from in the thread discussing about.
Also from signal strength, seems like the PA/LNA control is not working.
If possible I want to know where these numbers come from. May be DDFT mux registers info help to understand? Then where should I refer?
The register number is same as for CY8C4248 devices.
DDFT will be used as internally, so it is not disclosed in TRM.
Assume the module doesn't work but the project has been built successfully, is that correct?
If yes, please double-check hardware, especially pin mappings difference between 4248 and 214110 module. pin mappings must be kept consistent after the code ported to 4248.
The project built successfully also other many functions are working fine.
Only Power Antenna Control is not working.
I referred CYBLE-224110-00 and copied same pin mapping, and circuit designs.
As far as I know the difference between module and CY8C4248, CYBLE-224110-00 project doesn't show up control pins on creator(Pin3_1,Pin3_2), may be hidden by module specific configuration.
But 4248 can customize "Pin3_2" for CTX and "Pin3_3" for CRX. I've put pin components on PSoC Creators schematic window. Then set these pins as String Drive. Is this correct ?
Control output pins can be set as strong drive mode. The schematic could have some confidential info, please check your message box.
We checked the project. All seems to be doing all right. There could be some minor issue somewhere. Can you please check the project posted and check if P3.2 and P3.3 toggles for transmit & receive respectively?
I attached P3.2(CTX),P3.3(CRX) signal.
CH1.Yellow line is CTX, CH2 Blue Line is CRX.
I don't know about correct CTX control signal but compare to CRX seems like missing some control signal.
Connection interval is currently 8.75ms.
If slave misses master’s anchor point (does not sync on master’s TX), then it will not transmit and we see some yellow events (slaveTX) missing from the scope shot. It looks like the device failed to receive some packets from master, which resulted in the slave not responding back to the master (so missing TX)
So you mean this is normal behavior?
On Thu, Mar 5, 2020, 5:40 PM RuzheZ_36 <email@example.com>
Some times, a break in the return path of the RF signal can cause a high loss, which could result in poor RSSI.
Can you share the layout of BLE part with us to review?
We need to go production soon. Could you review schematic for electrically PA work.
Can I send you schematic through e-mail?