Polling the Psoc 4 status register

[smev_4172901]

having difficulty possible Polling   the status register as a flag. For bit banging and manipulation?

I have tried in both transparent and sticky mode with no success.

i did a pass through with the control write instruction and that seemed to work fine.

I was able to mirror the bit stream.

but otherwise i could not get anything to work with my code ..bit shifting and masking operations.

has anyone had any success with this.

[Rakesh_Patrudu]

Hi @smev_4172901 ,

Please be more specific about what status register you are referring to, as well as your application and please brief what you are trying to accomplish, so that we can provide a sample code for it. Please be detailed about which PSoC 4 device that you are using.

Best Regards,
Rakesh

[smev_4172901]

Hi I am  referring to the  Psoc 4 pioneer kit.

I have a Manchester decoded bit stream.

After decoding the Manchester encoded  stream via UDB logic.  As seen in this forum using a PWM.

I take the decoded clock and feed this into a UDB synch clock and then into the status register component clock input. with the data going into the input to the status register components input.

I then use polling to check when the status is  ready and set high . And if its set then i read this as a logic 1 else it is a zero. and wait a bit period before i check again.

I use the above to store the detected bits into a 16-bit variable and every bit test and validation I shift the bits one place left until i have 16-bits. I can then a do tests to see if i have found the start of a frame. If i have found the start I then continue collecting the data.

This is what I tried but i could not get it to work.

[BiBi_1928986]

Hello.

Which PSoC4 Pioneer kit?  There's more than a dozen of them.

Can you provide weblink for Manchester example you found on forum.  There are lots of them.

What is your data rate?  Is it possible the data is faster than the polling?

How do you know when to poll?
"I then use polling to check when the status is  ready and set high ."
What criteria are you using to decide if the Status Reg component is ready?
Are you using Status Reg component interrupts?