PSoc 4000 Arch TRM error?

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BiBi_1928986
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Looking at PSoC 4000 IMO clocking.  I'm using CY8C4013SXI-410.
In document:
PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D

it shows Table 8-1 for IMO frequency settings using register CLK_IMO_TRIM2 with a 6-bit field.  However, when referencing PSoC 4000 document:
PSoC 4 Registers TRM, Document No. 001-90002 Rev. *D
it shows a 3-bit field for CLK_IMO_TRIM2.

Which document is correct?

It looks to me like a copy/paste error from PSoC 4100/4200 doc's.  Or, I'm missing something.

Bill

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LinglingG_46
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CLK_IMO_TRIM2

In the register TRM is shows "3-bit field". That's right.

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LinglingG_46
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500 solutions authored 1000 replies posted 10 questions asked

CLK_IMO_TRIM2

In the register TRM is shows "3-bit field". That's right.

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Thank you.

This means Table 8-1 is incorrect for CLK_IMO_TRIM2.  Where can I find the correct table?

After reading more of the Registers documentation, CLK_IMO_TRIM2 is not used to set the IMO output frequency in 4MHz steps.  The correct register is called CLK_IMO_SELECT.  So, the text description in "PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D", section 8.2.1 Internal Main Oscillator, is referencing the wrong register.  Can you confirm this for me?  Thank you.

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