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Hi,
I'm using PSoC 4 board, I'm also using the WDT0 and WDT1 as the system timers as they work in the sleep mode, So I had to use the WDT2 as the system watchdog timer.
The WDT2 generates an interrupt when it fires, So I reset the system in the interrupt.
So, I disable the WDT2 when I'm going to sleep mode, and re-enable it after I wake up.
I found that the system sometimes could not enable the WDT2 and stuck in this excessive loop.
if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK))
{
while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2))
{
/* Wait for changes to come into effect */
}
}
I also found this comment
" * Enabling or disabling WDT requires 3 LFCLK cycles to come into effect.
* Therefore, the WDT enable state must not be changed more than once in
* that period."
So, I controlled the calls of CySysWdtEnable and CySysWdtDisable, and I made sure that they were not called within 3 LFCLK clocks, But this also did not solve the issue.
I also use a GPIO pin to measure the time between calling these functions(CySysWdtEnable, CySysWdtDisable), I found the minimum time is taken was 180us and the LFClK frequency was 32,768 kHz, So the 3 clocks should be 91.55us, So 180us should not makes any troubles.
So, If there are any solutions or guides to solve/avoid this issue will be very helpful.
Best Regards,
Khalil Azouz
Solved! Go to Solution.
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PSoC 4 MCU
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Hi @Khalil_Azouz ,
Please check if you are clearing the interrupt after ISR occurs from deep sleep:
Sleep or Deep-Sleep Mode: In this mode, the CPU subsystem is powered down. Therefore, the interrupt request from the WDT is directly sent to the WIC, which will then wake up the CPU. The CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
Thanks,
Krupashankar
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Hi @Khalil_Azouz ,
Could you please check if WDT_LOCK is cleared? Corruption in WDT may lead to set this bit so please clear it to generate interrupt.
Please refer to section 12.3.1 Enabling and Disabling WDT -> https://www.cypress.com/file/126171/download
Please let us know if this solves your issue?
Thanks,
Krupashankar
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Hi Krupashankar
Thanks for reply,
I checked the WDT_LOCK bits before enabling the WDT and made a condition to clear them each time they aren't, but this also did not solve the issue
Best Regards,
Khalil Azouz
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Hi @Khalil_Azouz ,
Please check if you are clearing the interrupt after ISR occurs from deep sleep:
Sleep or Deep-Sleep Mode: In this mode, the CPU subsystem is powered down. Therefore, the interrupt request from the WDT is directly sent to the WIC, which will then wake up the CPU. The CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
Thanks,
Krupashankar