PSoC4S : Reset process by WDT

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Dear Sirs and Madams,

 

Regarding the WDT reset, there is a difference between the set time on the GUI and the actual measurement time.

Since we have created a sample project, can you confirm the operation? ..

 

Software version : PSoC Creator 4.4

Device No. : CY8C4024PVA-S412

 

<About the reset occurrence time by WDT>
It is measured "NoUsePin_1" of the attached project.

・ Setting time on GUI: 204.8ms
・ Measurement time: 435.5ms

It seems that the WDT reset has not occurred in the set 204.8ms time.

We want to perform the microcomputer reset process when the WDT clear process CySysWdtClearInterrupt () is not performed.

Would you please confirm for this project?

 

Regards,

 

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8 Replies
Ronak
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 50 replies posted

Hello

Can you please explain on how you measured the time. Are you observing the reset at 435.5ms instead of the set time or its no reset at all.

Thanks,

Ronak

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Ronak-san,

Time is checking "NoUsePin_1" of the P4[0] pin.

 

In man.c,

First, this pin goes 'L' and initialize it.

Set this pin to 'H' after "CySys Wdt Enable" (before the infinite loop) .

this pin goes 'L' by WDT interrupt and soft reset.

 

High period of this pin is observed at 435.5ms.

We have set the WDT period to 204.8ms, but We don't understand why it is 435.5ms.

 

Regards,

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SudheeshK
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hello,

For a better understanding about this issue, could you please attach your project to this forum thread?

Thanks and Regards,

Sudheesh

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

 

Projects that can already reproduce the problem are attached to this thread.

We don't understand why the WDT timer interrupt does not set "NoUsePin_1" to'L' in a 204.8ms cycle.

Is there a problem with how we use the WDT?

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Do you have any update?

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Ronak
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 50 replies posted

Hello,

Can you please elaborate by which method you are setting the WDT period to 204.8ms in the project.

Regards,
Ronak

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RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

The WDT runs based on the ILO clock, which is not accurate. It is in range from 20 to 80 KHz (see SID237 in datasheet).

You can perform an ILO trimming to improve the accuracy of this clock, which will improve the accuracy of the watchdog. Refer to this code example:

https://www.cypress.com/documentation/code-examples/ce95329-compensation-ilo-trimming-psoc-4

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Ronak-san,

It is set in the "Timer (WDT)" of "Configure System Clocks" of the professional project attached to this thread.

MaMi_1205306_0-1627948132318.png

 

https://community.cypress.com/t5/PSoC-4-MCU/PSoC4S-Implementation-of-quot-CE224703-PSoC-4-Watchdog-T...

From the thread above, We understood that "Configure System Clocks" GUI settings are not enough and need to be set in the code.

 

Rodolfo-san,

We understand the ILO error.
However, I think that this problem depends not on the error but on the usage of WDT.
The reason is that discussing WDT in other threads and setting registers in the code will result in the intended behavior.

 

We've read the system reference guides, TRMs, datasheets, etc. and managed to get it working, but we can't tell if this configuration is really correct.

 

It would be nice to have an application note or sample project on how to configure the WDT without using  WDT component of PSoC4. PSoC4 has CE224703 but PSoC4S does not.

 

Regards,

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