We have a small design here with just a CY8C4244LQI-443 and an external RTC chip connected over SPI. The PSoC4200 enters hibernate mode when a pin is set to 0, using CySysPmHibernate(). Everything works as expected.
What we can see is that with low temperatures (below 0 degrees) the PSoC4 draws much more current that planned, the current gets from approx 1uA to over 60uA. With room temperature or higher, the current is always in a good range (1-2uA)
I tried to find any information about temperature dependency of hibernate mode in the documentation and errata, without success, maybe someone here can point me to a piece of information which could help.
I tracked down the internal Cypress characterization reports for PSoC4, including raw data files, and found that the mean current consumption in hibernate mode is about 80 nA, the standard deviation is 15 nA. This applies at all supply voltages. This certainly supports the spec. There are some possibilities. Is there a chance that you have condensation on your board? Have your boards been extensively cleaned so that condensation doesn't provide a current path? Are there other loads in parallel with the PSoC that might change at T < 0C?
My recommendation is to find at least two chips that fail your test, contact your local Infineon sales office and file a failure analysis request. We will get to the root of the problem.
---- Dennis Seguine, THE senior PSoC applications engineer
What RTC chip are you using? Any chance that they PSoC and RTC are wired together and you are measuring the sum?
Thanks for the hints @DennisS_46 , we use an RV-2123 RTC which consumes 170nA (measured). This doesn't change with temperature. The RTC pins (SPI and clock output, the latter being set to High-Z before entering hibernate mode) are connected to Port 0 on the PSoC and we will now try to remove it and set the inputs to the PSoC to 0 over 100kOhm resistors to make them defined, and measure again at -25°C.
Are there any electrical implications on inputs of the I/O freeze happening when hibernate mode is entered, so that some voltage levels on I/O ports can cause higher currents, or does that freeze only prevent input pin register changes or interrupts?
Can you send a copy of your project, by private email if you are concerned about security?
Please include enough of schematic so I can look at loads. I'll take a look. I have a call in to our product
engineering team following up on characterization data. I haven't heard back yet.