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NXTY_Tatebayasi
Level 5
Level 5
Distributor - NEXTY (Japan)
50 questions asked 25 likes received 250 sign-ins

Hi, Community,


Let me asked a question about how to set up the UART advanced tab.

I want to set the depth of the FIFO.
In this case, instead of putting a value in Tx Buffer, should I enter a variable in FIFO levels with Interruput enabled and the interrupt source selected as Tx FIFO level?

 

NXTY_Tatebayasi_0-1707379008972.png

Best Regards,

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1 Solution
MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

 -san,

 

As you know, you already understand that this FIFO of SCB is 16Bytes for both TX and RX.

However, I think you are making a simple mistake in the handling of "Byte".

 

Default is 8 elements of 16 bits, Byte mode is 16 elements of 8 bits.

Here, 1Byte is 8bits.

 

Default = 2Bytes x 8 elements = 16Bytes

Byte mode = 1Byte x 16 elements = 16Bytes

 

Or, since "4Byte = 16bits x 2 elements" cannot be set, we need to know the meaning of "the RAM area allocated for FIFO is 4 Bytes" that you are talking about.

If it's a UDB-based UART, the FIFO depth is certainly up to 4 Bytes...

MiNe_85951_0-1707475365222.png

 

As another thing that can be considered, there may be a possibility that the array specified in the main function is 4 bytes.

 

I hope your issue is resolved.

 

Regards,

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9 Replies
Rohan136
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes received

Hi @NXTY_Tatebayasi ,

Yes, you can enter the value of TX FIFO variable to trigger the interrupt whenever the number of data
elements (1 data element = 8 bits) in the TX FIFO is less than the value of TX FIFO level i.e. 8 data elements. I hope this answers your queries.

Let me know if you have more queries.

 

Regards,

Rohan

 

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NXTY_Tatebayasi
Level 5
Level 5
Distributor - NEXTY (Japan)
50 questions asked 25 likes received 250 sign-ins

@Rohan136 -san,

Thank you for your reply.

Unfortunately, the starting point of my question was incorrect.
The focus here should be FIFO depth, not FIFO level. Sorry about that.

I found FIFO depth discussed in this topic.
https://community.infineon.com/t5/PSoC-4/PSoC4100SP-SPI-FIFO-depth/m-p/147655#M21774

Am I correct in understanding that there are only two options for FIFO depth, Bytemode or not on PSoC4000S?
If there is a way to set the FIFO depth to any user desired value, please let me know.

Best Regards,

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hi,

 

FIFO depth is, as you know, 8 elements or 16 elements (Byte mode) in SCB.

However, by increasing the size of the TX/RX buffer, it is possible to stack data larger than the TX/RX FIFO in memory as a software buffer.

 

MiNe_85951_0-1707445638625.png

 

UDB only has a FIFO of up to 4 bytes, and if it exceeds that, it will be processed in a software buffer using internal interrupts.

 

Considering performance, a TX/RX Buffer size larger than FIFO is not very desirable, but if it is absolutely necessary to handle a larger amount of data, the method is to increase TX/RX Buffer size or DMA.

 

MiNe_85951_1-1707446479220.png

 

Also, I think there may be problems if the interrupt priority is not set high.

I've had trouble with this setting of UART(UDB) in the past.

 

For example, if you set the TX/RX buffer size to a value greater than 8, you will notice that DMA and FIFO not empty are grayed out, and interrupt are also configured internally only.

 

Regards,

NXTY_Tatebayasi
Level 5
Level 5
Distributor - NEXTY (Japan)
50 questions asked 25 likes received 250 sign-ins

Hi, @MiNe_85951 -san,

Thanks for your advice.

I guess the Tx Buffer size itself specifies the size allocated for the transmit data buffer, but no matter how much it is set, as soon as it is set, the RAM area allocated for FIFO is 4 Bytes.
In that case, there are only two elements that determine the FIFO depth, the default 8bit x 16 elements or the 16bit x 8 elements when set to the optional Byte mode, both of which are 4Byte as the RAM capacity.
The same size is allocated for the Rx Buffer.

Best Regards,

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hello  ,

 

I set the TX/RX Buffer size to 512 on UART (SCB) of PSoC4100S and tried building it in PSoC Creator , but no error occurred.

Also, regarding changing the TX/RX Buffer size, changing the Stack area and Heap area does not seem to affect the build.

 

I'm sorry that I don't fully understand your problem.

How did you confirm "the RAM area allocated for FIFO is 4 Bytes" that you say?

 

Regards,

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NXTY_Tatebayasi
Level 5
Level 5
Distributor - NEXTY (Japan)
50 questions asked 25 likes received 250 sign-ins

Hi, @MiNe_85951 -san,

Actually, the article says that the FIFO is 32Byte, with 16Byte allocated for each of Tx/Rx FIFO.
https://community.infineon.com/t5/Knowledge-Base-Articles/PSoC-4-MCU-FIFO-Size-of-PSoC-4-SCB-KBA2364...

So,I assumed that there was a FIFO split into the Tx Buffuer allocation and that it would be different size for each families.

Best Regards,

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

 -san,

 

As you know, you already understand that this FIFO of SCB is 16Bytes for both TX and RX.

However, I think you are making a simple mistake in the handling of "Byte".

 

Default is 8 elements of 16 bits, Byte mode is 16 elements of 8 bits.

Here, 1Byte is 8bits.

 

Default = 2Bytes x 8 elements = 16Bytes

Byte mode = 1Byte x 16 elements = 16Bytes

 

Or, since "4Byte = 16bits x 2 elements" cannot be set, we need to know the meaning of "the RAM area allocated for FIFO is 4 Bytes" that you are talking about.

If it's a UDB-based UART, the FIFO depth is certainly up to 4 Bytes...

MiNe_85951_0-1707475365222.png

 

As another thing that can be considered, there may be a possibility that the array specified in the main function is 4 bytes.

 

I hope your issue is resolved.

 

Regards,

NXTY_Tatebayasi
Level 5
Level 5
Distributor - NEXTY (Japan)
50 questions asked 25 likes received 250 sign-ins

Hello, @MiNe_85951 -san

Thank you very much for your great help !
Anyway, the FIFO depth is that I need my own research to understand.
I keep trying.

Best Regards,

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hi  ,

 

TX FIFO level settings are as follows :

MiNe_85951_0-1707395590381.png

The behavior of this configuration is that if you set the level to 4 as shown below, it will generate an interrupt when the FIFO falls below 4 data elements.

This FIFO level interrupt is used to request data before the FIFO reaches FIFO Full, which is 8 elements.

MiNe_85951_1-1707395672551.png

I often use FIFO Full and FIFO Empty, but I have never used this FIFO level.

 

When using multiple UART interrupts, you must mask the interrupt conditions and write the processing.

 

Regards,