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Regarding, the CY8CKIT-142 PSoC 4 BLE Module Schematic.pdf, looking at the psoc 4 ble module schematic as attached, the values of load cap C23 and C24 at 32.768KHz are 36pF and 18pF, so I'm wondering why used it differently, although I generally know by using the same load cap value.
Thank you!
Tony Kim
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Hi Tony Kim,
A higher C1/C2 ratio results in a higher current consumption but improved duty cycle. Based on extensive characterization, a ratio of 2:1 (C1= 2×C2) for the external capacitors is found to be optimal with respect to the performance and power consumption. The tradeoff for using a 2:1 ratio is slightly higher ICC (Integrated Chip Current) of up to 100 nA. For a 2:1 ratio, the recommended external capacitor values are: C1 = 37.5 pF, C2 = 18.75 pF (for CL = 12.5 pF) C1 = 18 pF, C2 = 9 pF (for CL = 6 pF).
For more information, please go through the following application note:
Thanks
Ganesh
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Hi Tony Kim,
A higher C1/C2 ratio results in a higher current consumption but improved duty cycle. Based on extensive characterization, a ratio of 2:1 (C1= 2×C2) for the external capacitors is found to be optimal with respect to the performance and power consumption. The tradeoff for using a 2:1 ratio is slightly higher ICC (Integrated Chip Current) of up to 100 nA. For a 2:1 ratio, the recommended external capacitor values are: C1 = 37.5 pF, C2 = 18.75 pF (for CL = 12.5 pF) C1 = 18 pF, C2 = 9 pF (for CL = 6 pF).
For more information, please go through the following application note:
Thanks
Ganesh