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PSoC™ 4

Li_Qiang
Level 4
50 replies posted 50 sign-ins 25 replies posted
Level 4

Hello:

我使用的芯片型号是CY8C4147LQS-S283,因为我想在MCU启动时重新配置一下所有管脚,所以做了下面一些管脚配置,但是当我把改好的程序烧写进MCU后,发现无法再用PSoC Creator进行调试,并且PSoC Programmer烧写时,提示错误“FAILED! PSoC device is not acquired! ” ,我做的管脚配置什么地方有错误吗,怎么才能重新烧写?

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P0, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P1, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P2, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P3, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P4, CYVAL_HSIOM_IO0_SEL_ACT_1);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL0, PDR00_P5, CYVAL_HSIOM_IO0_SEL_ACT_1);

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P0, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P1, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P2, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P3, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P4, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL1, PDR01_P7, CYVAL_HSIOM_IO0_SEL_GPIO);

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL2, PDR02_P3, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL2, PDR02_P4, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL2, PDR02_P5, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL2, PDR02_P6, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL2, PDR02_P7, CYVAL_HSIOM_IO0_SEL_GPIO);

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P0, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P1, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P4, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P5, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P6, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL3, PDR03_P7, CYVAL_HSIOM_IO0_SEL_GPIO);

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL4, PDR04_P0, CYVAL_HSIOM_IO0_SEL_ACT_1);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL4, PDR04_P1, CYVAL_HSIOM_IO0_SEL_ACT_1);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL4, PDR04_P2, CYVAL_HSIOM_IO0_SEL_ACT_1);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL4, PDR04_P3, CYVAL_HSIOM_IO0_SEL_ACT_1);

CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL6, PDR06_P0, CYVAL_HSIOM_IO0_SEL_GPIO);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL6, PDR06_P1, CYVAL_HSIOM_IO0_SEL_ACT_3);
CY_SYS_PINS_HSIOM_MODE(CYREG_HSIOM_PORT_SEL6, PDR06_P2, CYVAL_HSIOM_IO0_SEL_ACT_3);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P0, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P1, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P2, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P3, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P4, CY_SYS_PINS_DM_DIG_HIZ);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT0_PC, PDR00_P5, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P0, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P1, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P2, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P3, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P4, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT1_PC, PDR01_P7, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT2_PC, PDR02_P3, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT2_PC, PDR02_P4, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT2_PC, PDR02_P5, CY_SYS_PINS_DM_DIG_HIZ);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT2_PC, PDR02_P6, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT2_PC, PDR02_P7, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P0, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P1, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P4, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P5, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P6, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT3_PC, PDR03_P7, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT4_PC, PDR04_P0, CY_SYS_PINS_DM_DIG_HIZ);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT4_PC, PDR04_P1, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT4_PC, PDR04_P2, CY_SYS_PINS_DM_DIG_HIZ);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT4_PC, PDR04_P3, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT6_PC, PDR06_P0, CY_SYS_PINS_DM_STRONG);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT6_PC, PDR06_P1, CY_SYS_PINS_DM_DIG_HIZ);
CY_SYS_PINS_SET_DRIVE_MODE(CYREG_GPIO_PRT6_PC, PDR06_P2, CY_SYS_PINS_DM_STRONG);

CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT0_DR, PDR00_P0, CY_SYS_PINS_DR_INIT_DATA);

CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P0, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P1, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P2, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P3, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P4, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT1_DR, PDR01_P7, CY_SYS_PINS_DR_INIT_DATA);

CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT2_DR, PDR02_P3, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT2_DR, PDR02_P4, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT2_DR, PDR02_P6, CY_SYS_PINS_DR_INIT_DATA);

CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P0, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P1, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P4, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P5, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P6, CY_SYS_PINS_DR_INIT_DATA);
CY_SYS_PINS_DR_SET(CYREG_GPIO_PRT3_DR, PDR03_P7, CY_SYS_PINS_DR_INIT_DATA);

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1 Solution
Li_Qiang
Level 4
50 replies posted 50 sign-ins 25 replies posted
Level 4

Hello.

现在问题已经解决了,因为我使用的硬件设备中PSoC是外部供电,所以我将烧写线单独引出,使烧写器能够给PSoC供电,在PSoC programmer中设置Power Cycle模式就可以重新烧写了。

View solution in original post

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3 Replies
LinglingG_46
Moderator
Moderator 750 replies posted First comment on KBA 500 replies posted
Moderator

1: 你是在哪个平台上面开发的?

2:你哟个的这个函数是PSoC Creator, MTB底层生成的库吗?

3:你为什么要对这些GPIO做这样的配置?你配置的依据是什么?

4:目前你的芯片是否损坏?

5:你是想实现一个什么功能?

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Li_Qiang
Level 4
50 replies posted 50 sign-ins 25 replies posted
Level 4

多谢回复,我已经发现SWD管脚被我错误的配置了,导致我无法用PSoC programmer和PSoC Creator进行烧写了,我想咨询一下,这种情况可以重新刷新程序吗,因为到目前为止,我用PSoC programmer烧写一直没有成功过,提示“PSoC device is not acquired”错误。

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Li_Qiang
Level 4
50 replies posted 50 sign-ins 25 replies posted
Level 4

Hello.

现在问题已经解决了,因为我使用的硬件设备中PSoC是外部供电,所以我将烧写线单独引出,使烧写器能够给PSoC供电,在PSoC programmer中设置Power Cycle模式就可以重新烧写了。

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