PSoC I²C Ultra Fast Mode

[KaiG]

Dear Community,

I am trying to set up my first I²C BUS with an CY8CKIT-04 of the 4M-Series. I think I understood the provided example program and was able to work with it.

Now I am limited by the data rate of 1000 kbps which seems to be the Fast Mode Plus.

Is there any way to realize the 5 MHz Ultra-Fast-Mode of I²C with any PSoC Devise?

If it is not possible, do you have any recommendations for faster Communication between PSoCs?

Thanks in advance.

[MotooTanaka]

Hi,

Although I have not tried I2C with 5MHz, in case it does not work,

I would try to use SPI which should work faster than 5MHz.

moto

[KaiG]

Thanks for the information,

I guess I will give SPI a try.

My main issue with I²C is, that I can`t Build my project with higher bit rates than 1000 kbps.

So I guess its not intended.

[MotooTanaka]

Hi,

I wonder if you can configure I2C module with clock input.

Then you can assign higher clock to the clock pin,

I don't know if it will work or not though.

moto

[PandaS · Accepted solution]

Hi @KaiG ,

You are right, PSoC4 only supports  Slow-mode (50 kbps), standard-mode (100 kbps), fast-mode (400 kbps), and fast-mode plus (1000 kbps) data-rates in I2C communication. For your application its better to go for SPI protocol.

Warm Regards

Sobhit

[KaiG]

Hi,

I tried so. In the picture of the previous message, I checked the Box “Clock from terminal”. I connected a 48 MHz clock to the shown pin an the I2C component calculates a data rate of 4000 kbps.

The error which shows up next to the actual data rate of 4000 kbps says “the data rate value must be between 1 and 1000 kbps”.

I guess I can`t use over 1000 kbps unless there is a trick to speed the Component up.

Kai

[Len_CONSULTRON]

Kai,

Effectively you can technically use higher clock rates than 1000 Kbps by using the external clock method.

However in the I2C world there are some technical limits you should be aware of.

The I2C standards group defined multiple data rates for masters and slaves.  At each data rate, there is  limit on the load capacitance and the pull-up bias resistor.

Generally, as the data rate goes up the lower the load capacitance and bias resistance on the SDA and SCK are allowed.

This is because the SDA line is shared and needs to be bi-directional.  To achieve this, all the drivers on this line is configured as an open-drain drive low, float high.  The bias pull-up resistor is what pulls the signal high when no driver on the line is turned on.

Since a '0' signal drives low, the fall time can be reasonably fast (<20ns).  However a '1' signal floats high with the pull-up and together with the load capacitance can be much slower rise time.

As a rule-of-thumb, I target no more than 10% of the SCK period to be rise time + fall time.

Let's say you are targeting a SCK of 1MHz.  This means the period is 1000ns.  Using 10% of 1000ns (=100ns) and a fall time of 20ns. this leave only 80ns for rise time. 

If your load capacitance is a max of 100pF this means your R*C time to achieve less than 80ns is:

80ns = R*C => 80 * 10^-9 = R * (100 * 10^-12) => R = 800 ohms   [R is the value of the pull-up resistor)

If you're bias voltage is 5V then this means driver on the line when driving low must be able to sink (5V/800 ohm 😃 6.3 mA.  This is possible.

However as the data rates go up, the bias pull-up resistor value goes down which will require higher driver sink current.

You are trying to target 4MHz as your data rate.

This means that the clock period is 250ns.  Using my 10% rule, this means you can afford 25ns of rise and fall time.  If your driver is good enough to achieve 10ns fall time, then you are left with 15ns for rise time.

Assuming you can get a load capacitance of 50pF this means your pull-up needs to be 

15 * 10^-9 = R * (50 * 10^-12) => R = 300 ohms.

At 300 ohms your driver needs to sink 16.7mA.   Doable but not ideal.  The chart I supplied shows that it is recommended for this data rate to use a push/pull configuration for the drivers to create a much faster rise time.