Greetings - The PSoC 4 Arch TRM mentions in section 8.3.4 Peripheral Clock Configuration that the "peripheral clocks, including the analog SAR clock, are sourced by peripheral clock dividers. Each divider input can be used to generate two versions of the clock: a gated clock and a divided clock."
How would gated vs divided be configured/controlled?
PSoC 4 MCU
When using PSoC Creator to configure the clocks, you can see the clocks used in your design by clicking on the clocks tab under Design wide resources:
Here, you would also find the Edit Clock option which can be used to set the frequency of your system clocks as can be seen in the image below:
PSoC 4200 has the following clock tree, according to which HFCLK can be routed to different peripheral dividers to produce clock of appropriate frequency:
In PSoC Creator when using any component, mostly there will be an option to connect an external clock. This can be used by the user to configure the clock for components themselves. For example, when using a SAR ADC, the component has an option to connect a clock externally, the clock component can be used to configure the frequency of the input clock. As can be seen, there are options to specify divider/fractional divider for the input clock used by the component. This internally uses the peripheral clock dividers mentioned by you.
Ekta - thank you for all the great info, but I was more specifically looking for how to control the clk_gated vs clk_divided as shown in show here (from the TRM):