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CyCP
Level 2
Level 2
5 replies posted 10 sign-ins 5 sign-ins

Hi,

As per ARM documentation, Cortex-M0 LDR/STR instructions should take 2 cycles for execution. This is usually honored by the PsoC 4 MCUs, but, while accessing GPIO pins, they take 6 cycles. I am not able to find any document describing it.

Could you please help me on this?

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1 Solution
BiBi_1928986
Level 7
Level 7
First comment on blog 500 replies posted 250 replies posted

Hello.

This topic has been addressed many-many times in the past.  You won't find any Cypress documentation on this because its ARM Cortex-M0 documentation that you need to refer to.  Visit their web site.

Forum discussions illustrated that it takes 5 clock cycles to perform a write to GPIO port pin.
Solved: Re: Bitbanging Cycle Count - Infineon Developer Community
I don't have cycle numbers for GPIO input direction.

The main reason it takes longer than 2 cycles, is because the ARM core operates on its internal AHB bus and that has to be synchronized with the internal MMIO peripheral bus.  The synchronization process can take additional clock cycles, meanwhile the ARM core is stalled out waiting for the transaction to complete.

Another factor is the FLASH.  Zero wait state access is limited to slower ARM core clock speed.  With a built-in FLASH accelerator, yes, zero wait state access speed is sometimes available.

PSoC 4 has the ARM core 3-stage instruction pipeline.  This can also cause additional clock cycles if it needs to be flushed to fetch the next instruction.

Then there's the GPIO output latch that needs to be clocked.  Yet another clock cycle.

PSoC 4 will behave slightly differently from a PSoC 5LP due to architecture differences.  The above discussion relates to PSoC 4.  Here's a good video explaining PSoC 5 GPIO access clock cycles if interested.
C++ vs Assembly vs Verilog. on Vimeo

As a note:
Additional clock cycles aren't limited to Cypress ARM devices.  I'm not aware of any ARM devices that don't incur extra clock cycles in order to access their I/O capabilities.

Good luck with your project.

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2 Replies
BiBi_1928986
Level 7
Level 7
First comment on blog 500 replies posted 250 replies posted

Hello.

This topic has been addressed many-many times in the past.  You won't find any Cypress documentation on this because its ARM Cortex-M0 documentation that you need to refer to.  Visit their web site.

Forum discussions illustrated that it takes 5 clock cycles to perform a write to GPIO port pin.
Solved: Re: Bitbanging Cycle Count - Infineon Developer Community
I don't have cycle numbers for GPIO input direction.

The main reason it takes longer than 2 cycles, is because the ARM core operates on its internal AHB bus and that has to be synchronized with the internal MMIO peripheral bus.  The synchronization process can take additional clock cycles, meanwhile the ARM core is stalled out waiting for the transaction to complete.

Another factor is the FLASH.  Zero wait state access is limited to slower ARM core clock speed.  With a built-in FLASH accelerator, yes, zero wait state access speed is sometimes available.

PSoC 4 has the ARM core 3-stage instruction pipeline.  This can also cause additional clock cycles if it needs to be flushed to fetch the next instruction.

Then there's the GPIO output latch that needs to be clocked.  Yet another clock cycle.

PSoC 4 will behave slightly differently from a PSoC 5LP due to architecture differences.  The above discussion relates to PSoC 4.  Here's a good video explaining PSoC 5 GPIO access clock cycles if interested.
C++ vs Assembly vs Verilog. on Vimeo

As a note:
Additional clock cycles aren't limited to Cypress ARM devices.  I'm not aware of any ARM devices that don't incur extra clock cycles in order to access their I/O capabilities.

Good luck with your project.

CyCP
Level 2
Level 2
5 replies posted 10 sign-ins 5 sign-ins

Hi,

thank you very much.

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