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PSoC™ 4 Forum Discussions

Anonymous
Not applicable

Hello:

   

 

   

Does anyone know what the interrupt latency is for the PSoC 4?  I am running a 4200 with an external 48MHz clock.  When I trigger an interrupt with a timer compare, there is an 800ns delay  before the ISR toggles an output line.  I am using a register write, not one of the generated functions.  My understanding was that latency for M0 was 16 cycles.  If that was the case, the delay would only be about 350ns.  Am I doing something wrong, or are interrupts slow on this MCU?

   

A search of the data sheet and technical reference manual did not reveal any answers.

   

 

   

Thanks,

   

Stephen

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ETRO_SSN583
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Other than the obvious, eg. you have the interrupt priority at highest,

   

I saw this in ARM manual, attached.

   

 

   

Regards, Dana.

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Anonymous
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Thanks for the reply.

   

With regards to the posted jpg image titled Interrupt Latency:

   

To be sure I am only dealing with one interrupt, I created a separate project that just has a single counter setup with a compare.  The cc ouput goes to a GPIO line, and the ISR toggles another GPIO line.

   

The measured time between the two pulses (trailing edge of cc output and leading edge of ISR-toggled line) now is about 650ns.  I know there are a few cycles needed to execute the line toggle, but that still seems high.

   

There is no mention of wait states for RAM in the literature, and to further rule wait states out as a cause for slowing things down, I tried reducing the clocking by a factor of 2, and that exactly doubled the latency I was getting at 48MHz, which implies the number of CPU clock cycles needed for the interrupt is the same.

   

Poking around in Creator, I don't see any options for setting IRQLATENCY to disable the zero jitter feature, and further, don't see any mention of it in the literature.  I don't see any jitter on the second pulse, so I wonder if that is why the ISR latency is so high?

   

Thanks,

   

Stephen

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ETRO_SSN583
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Page 10, 11 of this ap note may help. Toggling GPIO......

   

 

   

http://www.cypress.com/?rID=57571    AN72382

   

 

   

For PSOC 3 / 5LP, but should apply to PSOC 4 as well.

   

 

   

Clearly in ISR keep from doing f() calls, stack push, etc.. will slow you down.

   

 

   

Regards, dana.

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Anonymous
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Hi All,

   

The minimum interrupt latency which can be obtained in PSoC 4 at 48 MHz CPU frequency is around 600 ns (29 cycles). It is not possible to achieve a lower latency than this.

   

This minimum latency can be achieved only by placing all the interrupt related functions (including interrupt service routine) in SRAM. The functions can be located in SRAM using the attribute keyword in their declaration. For example:

   

void isr_Start(void) __attribute__ (section(".data");

   

 

   

Regards,

   

Asha

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Anonymous
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Hi Asha,

   

Thanks very much for the information.  I do have one question: I can understand why placing the ISR in RAM would affect the performance of interrupts, but why do functions like isr_Start() need to be placed there as well?

   

Thanks,

   

Stephen

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HeLi_263931
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isr_Start() _is_ the ISR...

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Anonymous
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>isr_Start() _is_ the ISR...

   

It doesn't look that way to me... I have this generated code, where Timer0_ISR_Interrupt() is the ISR.  The Start function enables, sets priority, and the vector (Timer0_ISR_Interrupt), as shown below:

   

 

   

/*******************************************************************************
* Function Name: Timer0_ISR_Start
********************************************************************************
*
* Summary:
*  Set up the interrupt and enable it.
*
* Parameters: 
*   None
*
* Return:
*   None
*
*******************************************************************************/
void Timer0_ISR_Start(void)
{
    /* For all we know the interrupt is active. */
    Timer0_ISR_Disable();

    /* Set the ISR to point to the Timer0_ISR Interrupt. */
    Timer0_ISR_SetVector(&Timer0_ISR_Interrupt);

    /* Set the priority. */
    Timer0_ISR_SetPriority((uint8)Timer0_ISR_INTC_PRIOR_NUMBER);

    /* Enable it. */
    Timer0_ISR_Enable();
}

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HeLi_263931
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I think Asha meant with his example ther ISR, even though the method name might not reflect this. Its just the ISR which needs to be in RAM.

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Anonymous
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I see, thanks,

   

Stephen

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Anonymous
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The ISR that is generated by the compiler will have the generic name that you describe, but if you disable or use your own ISR, then you can give it any name you want. Two different ways to implement the same thing essentially.

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