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Hello, I am using the Cy8C4244PVI-442 PSOC 4 MCU and have configured it for 5V supply:
I want to know what will be the output voltage level of the output pins.
I'm looking on page 21 of the datasheet:
Correct me if I'm wrong, but the output voltage for a logic high would be from 3V to 5V.
Am I correct?
Thank you
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PSoC 4 MCU
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joli,
I realize it is a bit confusing but let me try to simplify.
In general, Voh is VDDD-0.6V up to VDDD (output current load = 4mA). If VDDD = 5V then the Voh(min @ Ioh = 4mA) = 4.4V.
If your current load is only 1mA then Voh is VDDD-0.5V up to VDDD. If VDDD = 5V then the Voh(min @ Ioh = 1mA) = 4.5V.
"Engineering is an Art. The Art of Compromise."
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joli,
I realize it is a bit confusing but let me try to simplify.
In general, Voh is VDDD-0.6V up to VDDD (output current load = 4mA). If VDDD = 5V then the Voh(min @ Ioh = 4mA) = 4.4V.
If your current load is only 1mA then Voh is VDDD-0.5V up to VDDD. If VDDD = 5V then the Voh(min @ Ioh = 1mA) = 4.5V.
"Engineering is an Art. The Art of Compromise."
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Thank you very much.
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joli,
You're welcome.
Actually I have better news for you.
For you with VDDD at 5V, Voh will probably be much better. The actual Voh (with VDDD = 5V Ioh= 1mA) will be closer to VDDD - 0.2V or even VDDD - 0.1V. This is because the higher VDDD voltage can drive the gate of the output with more voltage lowering the Rds_on of the high FET supplying Voh.
The spec you quoted (SID60) is Voh (with VDDD = 1.8V Ioh = 1mA). This provides a Rds_on of (0.5V/1mA) 500 ohms. At VDDD = 5V the Rds_on is probably closer to 150 ohms.
If you stay with VDDD-0.5V for worst-case, you should be safe.
Additionally, you can parallel GPIO outputs to get increased source/sink current. This is better if they're on the same port.
"Engineering is an Art. The Art of Compromise."