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bikerglen
Level 1
Level 1
First solution authored First reply posted First question asked

Hi,

I'm trying to use the PSOC Sensei's FIFOin component in polled mode on a PSOC 4 4200M CPU.

According to the datasheet, I should be able to enable the FIFO, check the status byte to see if it is not empty, and then read the head of the FIFO using the calls FIFOIn_1_Start(), FIFOIn_1_ReadStatus (), and FIFOIn_1_Read () respectively.

I call Start, I call ReadStatus in a tight loop until bit 1 (0x02) is set indicating the FIFO is not empty, but then when I  call Read, my program hangs.

Any ideas why calling FIFOIn_1_Read () would cause the micro to hang? Is the PSOC Sensei FIFOin component incompatible with PSOC 4? If so, is there any way to fix it?

I attached an archive of my workspace / project. It needs the FIFOin from this post added in as a dependency to compile.

https://community.cypress.com/t5/PSoC-5-3-1-MCU/Difficulties-using-the-parallel-input-bus-PI-in-UDBs...

I've never used a Cypress PSOC before so I'm trying the simplest possible way to pass data from my Verilog component to my software. The Verilog component just writes 'dead' to the FIFO at 4.096kHz then I'm trying to poll the status and fifo data registers to read them.

Thanks,
Glen

 

 

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bikerglen
Level 1
Level 1
First solution authored First reply posted First question asked

Figured it out. There's a bug in FIFOin_1.c. Line 175 should be

return(CY_GET_REG16(FIFOIn_1_FIFO16_PTR));

The '16' is missing on the version on the Infineon/Cypress website.

-Glen

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bikerglen
Level 1
Level 1
First solution authored First reply posted First question asked

Figured it out. There's a bug in FIFOin_1.c. Line 175 should be

return(CY_GET_REG16(FIFOIn_1_FIFO16_PTR));

The '16' is missing on the version on the Infineon/Cypress website.

-Glen

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