Nice factoid in the PSOC 4 -
The PSoC 4100/4200 includes a hardware multiplier that
provides a 32-bit result in one cycle.
Maybe this will go a long way to FIR and IIR w/o DFB, although latter clearly
This is not too shabby -
SARSEQ is a dedicated sequencer controller that automatically sequences the input mux from one channel to the next
while placing the result in an array of registers, one per
■ Control SARMUX analog routing automatically without
■ Control SAR ADC core (such as resolution, acquisition
time, and reference)
■ Receive data from SAR ADC and pre-process (average,
■ Results are double-buffered so the CPU can safely read
the results of the last scan while the next scan is in progress.
The features of SARSEQ are:
■ Eight channels can be individually enabled as an automatic scan without CPU intervention
■ A ninth channel (injection channel) for infrequent signal
to insert in an automatic scan
■ Per channel selectable
❐ Input from external pin or internal signal (AMUXBUS/
❐ Up to four programmable acquisition time
❐ Default 12-bit resolution, selectable alternate resolution: either 8-bit or 10-bit
❐ Single-ended or differential mode
❐ Result averaging
I thought the SARMUX is like the already existing component on the 5LP, but it seems much more capable. Looks really nice. Unfortunately, without DMA the high sample rate cannot really be used.
The PSoC5 already has hardware multiple (even divide) since its standard on the Cortex-M3 (see http://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M3 or http://www.arm.com/products/processors/cortex-m/cortex-m3.php?tab=Specifications )
EZI2C seems to be in hardware now too. The whole communication interface stuff is in hardware now - this will really free up resources when they are used.
The multiplier on a $ 1 part is what is significant.
I saw this in TRM, DMA, maybe the families with expanded FLASH and UDBs will
have DMA, or is this just a cut and paste from PSOC 3/5....
PLD Macrocell Read-Only Registers
The outputs of the eight macrocells in the two PLDs can be accessed by the CPU/DMA as an 8-bit read-only register. Macro
cells across multiple UDBs can be accessed as 16 or 32-bit read-only registers. See UDB Addressing on page 160.
The mentioning of DMA seems to be a copy-paste error. It is nowhere else specified - and it should have its own section in the TRM when it would exist.
The 4100 has no UDBs? Then its just a MCU like all the other ones out there, with maybe some nicer peripherals. OK, then there is Creator to make programming it easier, but still...
Oh, and there are finally prices: $1.36 for the smallest 4100 (in 1000+ quantity), and $2.52 in single quantities for the largest 4200. But they are all out of stock...
4 32-bit-counters? The data sheets shows only 4 timers with 16 bits each. Are the upper 16 bits done in hardware?
Apart from that - compare the feature set with e.g. the lowest dsPIC33F chips. They are really comparable, and without the programmable block the PSoC4 loses its greatest advantage. And even with that Cypress doesn't reach the $1 goal...
(It's not that I don't like the PSoCs, but I love them for their flexibility, and the 4100 series is not the PSoC I know and love)
The resource table vs cntr bit width shows 35 macrocells being used, so
I take that to be HW solution for all 32 bits. And module datasheet does not
indicate anything to the contrary.
Looking at lowest pin count dsPIC33F the pricing seems to be
in $ 2 range. That of course is only part of the picture. Clearly
a side by side analysis is what most EE departments use, including
things like maturity, device geometry, features, price, tools, are what
generally determine large volume decisions.
And lest we forget, actual device/family introductions not infrequently
driven by specific high volume designs and requirements at key
customers, 5 - 10M pieces, this of course we are not in the privileged
But the 4100 has only 32 macrocells (4 UDBs with 2 PLDs each, with 4 MCs each). When I try to test that, I get the error message "Maximum number of UDB macrocells exceeded", I cannot even place a _single_ 32 bit counter and compile it for the 4100 (tested with both basic counter and the normal counter).
For my tests, I started with an empty 4100 project, which select a CY8C4125AXI-483.
So now I'm officially confused...
I found in workspace explorer the 32 bit counters do not show up
with any associated APIs, serious problems. I will ed.keep forum
Response from Cypress is Creator has an error showing fix function
UDB based counters in 4100. SW team will update Creator to not
show modules not available in PSOC 4 in next release.
But this still leaves open the question how you did manage to get 4 32bit counter into a PSoC? Right now I see only the TCPWM component available for the PSoC4 (all other counter components use UDBs), and it goes only up to 16 bit...
Actually in build I never got 4 32 bit counters, they were all optimized
out as there was no UDB array to provide the PLD's needed.
Now thats strange too - because when I tested it Creator complained that it has not enought UDBs available. But then I connected it to some IO-Pins, so it could not be optimized ouz...