On the PSoC4200L, which ports can UDB-based digital signals be routed to?

[NXTY_Inoue]

Dear Sir,

I would like to confirm the description of "3.2.Pin Routing" in AN86439.

https://www.infineon.com/dgdl/Infineon-AN86439_PSoC_4_Using_GPIO_Pins-ApplicationNotes-v12_00-EN.PDF...

I found the explanation below.

It is explained here that port 10(port7 to port10) cannot be routed for UDB digital signals.

This is not the same as the datasheet. Datasheet is below.

Actually, I tried the operation by using PsoC Creator.

It was possible to route to port 10.

Is AN86439 a mistake?

[DennisS_46]

AN86439 is not wrong. It says that UDB-based signals can't be routed to some of the ports because the DSI (digital signal interface) doesn't go there. The signals that you routed to P10.0 is from the TCPWM block, not from UDBs. TCPWM signals route only to specific places. UDB signals have fewer routing restrictions in the ports that they go to, but they don't go to all ports.

---- Dennis Seguine, PSoC Applications Engineer

[NXTY_Inoue]

Thank you for your help.

I tried it in another project.
I placed the logic circuit and routed the output to P10.7.
The report is below.

It looks like UDB is being used and I can build this project.

am i doing something wrong?

Furthermore, I would like to confirm why the explanation in the datasheet and the application note are different.

If the application note is correct, is the datasheet incorrect?

[DennisS_46 · Accepted solution]

I made an error, AN86439 is wrong, this and other documents have errors:
Datasheet 001-91686 page 8 says UDBs can connect to any port except 7,8,9.
App note 001-86439 page 14 says any port except 7 - 10.
Architecture TRM 001-97952 page 69 says no UDBs to port 7-10.
Registers TRM 001-98126 ducks the whole issue and says look at the Architecture TRM.
I had to go back to the governing document, called the SASS. Its spreadsheet shows
no UDB connections to port 7, 8,9 and UDB connections available to port 10.
So, the datasheet is correct. PSoC Creator allows UDBs to port 10, this is correct.
I built a project that proves it. I don't have a suitable kit in my lab, but it built and the DWR pins view shows up as expected. That's good  enough for me.
Thus, we have two important documents (AN and Arch TRM) that are incorrect, and the
registers TRM that ignores the subject.
A A R R R GH.
I had a lot of help in finding this. I am truly sorry that you wasted your time on our bad
documentation. I will get the documents fixed.
If I can provide any other assistance, please let me know.
---- Dennis Seguine (THE senior PSoC applications engineer (since August, 2000))

[NXTY_Inoue]

Dir sir,

This problem was resolved thanks to your support.

Inoue

[DennisS_46]

Thanks for spotting the error. Internal defect tracking tickets have been submitted; errors will be fixed in next revision.
---- Dennis