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Due to unavailability of 212019 we must migrate an existing design to 214015, which is available. We found no way to use the SCB in SPI-Mode because SCBx_CLK can only be output to P0.7 which is used for debugging. Is it correct that the 214015 has a dedicated SPI_Master which is not mentioned in the datasheet but the outputs can be routed to any GPIO ( or is it a UDB used for that )?
Also for using CapSense, in 212019 we had to add a capacitor to Cmod (P4.0) which is not present in the 214015 but the Port 4.0 appears in the Pin-List (33 of 32) of the creator. Is it an internal Pin of the module, which is in turn connected to this 2n2-capacitor?
Would be nice to have this clear before making new PCB's
Thanks
Solved! Go to Solution.
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If you choose the "CapSense CSD", it only be config to P4.0.
Because the component is the old version compared with "CapSense".
This is due to product development.
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If you want to use the SCB SPI master, you can change the debug interface from SWD to GPIO, you also can use the UDB SPI, then you can config the clock pin to other pins.
You can config the Cmod to other pin like: P2.1.
It is convient for us to create a project in PSoC Creator to check the hardware resource, I add the test project in attachment.
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Thank you for your post. I see Cmod can be routed to P2.1 for the Capsens module but not for the CapSense CSD module. As you can see in the snapshot as soon as i choose CapSense CSD block only P4.0 is available and this on pin 33 which is not present on package. The project is your project with exchanged Capsense to CapSense CSD.
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If you choose the "CapSense CSD", it only be config to P4.0.
Because the component is the old version compared with "CapSense".
This is due to product development.