Hello,
I'm relatively new to the PSOC chip so I would appreciate some guidance. I working on a design that needs to have an extremely low inactive power consumption. We currently targeting the 4200 series and I'm currently developing with the CY8C4245 but that's subject t to change as needed.
We need timer which fires once per hour with ~+/-10% long term accuracy. We'll be in the Deep Sleep mode so the ILO will be active. I plan to calibrate the ILO once per hour using the IMO as a reference during the wake up time. Hopefully the 2% IMO will enable us to calibrate the ILO to something on the order of 10% accuracy. Our product are mostly be used indoors so the temperature will be relatively constant.
I see two possible approaches. The first would be to use the RTC. It looks like the RTC wakes the main processor once per second to increment a counter in firmware. The RTC is overkill for our needs but power draw is is most important parameter. Since the RTC is a firmware implementation, it seems hard to estimate the current draw and I didn't see a spec for it anywhere.
The second approach would be t use a UDB counter. A 32-bit counter with a period of 155,200,000 would generate an IRQ once per hour from the 32kHz ILO. I could adjust the counter period on the fly to calibrate the clock. The 32 bit counter is spec'd at 32 uA/MHz which would be right a 1uA assuming the spec's is still accurate at the low a frequency. A 16 bit counter could generate an IRQ every 2 seconds at an ~0.5 uA consumption but I suspect the extra power consumed by waking more frequently would outweigh the lower power gains.
Any guidance that you can offer would be appreciated. My instinct is that the UDB counter approach is the best option but I'm opening to anything at this point.
Sincerely,
Ben Wirz
Element Products, Inc.
