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PSoC™ 4

benwirz
Level 1
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Level 1

Hello,

I'm relatively new to the PSOC chip so I would appreciate some guidance.  I working on a design that needs to have an extremely low inactive power consumption.   We currently targeting the 4200 series and I'm currently developing with the CY8C4245 but that's subject t to change as needed.

We need timer which fires once per hour with ~+/-10% long term accuracy.   We'll be in the Deep Sleep mode so the ILO will be active.   I plan to calibrate the ILO once per hour using the IMO as a reference during the wake up time.  Hopefully the 2% IMO will enable us to calibrate the ILO to something on the order of 10% accuracy.     Our product are mostly be used indoors so the temperature will be relatively constant.

I see two possible approaches.  The first would be to use the RTC.   It looks like the RTC wakes the main processor once per second to increment a  counter in firmware.  The RTC is overkill for our needs but power draw is is most important parameter.   Since the RTC is a firmware implementation, it seems hard to estimate the current draw and I didn't see a spec for it anywhere.   

The second approach would be t use a UDB counter.  A 32-bit counter with a  period of 155,200,000 would generate an IRQ once per hour from the 32kHz ILO.   I could adjust the counter period on the fly to calibrate the clock.   The 32 bit counter is spec'd at 32 uA/MHz which would be right a 1uA assuming the spec's is still accurate at the low a frequency.   A 16 bit counter could generate an IRQ every 2 seconds at an ~0.5 uA consumption but I suspect the extra power consumed by waking more frequently would outweigh the lower power gains.

Any guidance that you can offer would be appreciated. My instinct is that the UDB counter approach is the best option but I'm opening to anything at this point. 

Sincerely,

Ben Wirz
Element Products, Inc.

 

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Ekta
Moderator
Moderator 250 solutions authored 100 likes received 250 sign-ins
Moderator

Hello Ben,

If you are planning to use the UDB based counter you wont be able to use the counter in Deep Sleep mode.

You can refer to the PSoC 4 Low-Power Modes and Power Reduction Techniques , which mentions that UDB are in retention in the Deep Sleep mode.

Ekta_0-1612530206320.png

Which means that the state of the peripheral is retained however the peripheral will continue its operation when the device enters active mode.

If it is required by your application to consume less power by moving into the deep sleep mode, I would suggest you to use the RTC in your application.

Kindly let me know in case of further clarifications.

Best Regards

Ekta

 

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Ekta
Moderator
Moderator 250 solutions authored 100 likes received 250 sign-ins
Moderator

Hello Ben,

If you are planning to use the UDB based counter you wont be able to use the counter in Deep Sleep mode.

You can refer to the PSoC 4 Low-Power Modes and Power Reduction Techniques , which mentions that UDB are in retention in the Deep Sleep mode.

Ekta_0-1612530206320.png

Which means that the state of the peripheral is retained however the peripheral will continue its operation when the device enters active mode.

If it is required by your application to consume less power by moving into the deep sleep mode, I would suggest you to use the RTC in your application.

Kindly let me know in case of further clarifications.

Best Regards

Ekta

 

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PSa_795526
Level 4
First like given 10 replies posted 5 solutions authored
Level 4

Hi Ben,

You can also consider using the Watchdog timer block in the PSoC 4200/4100 devices to generate period in hours from the low power ILO in deep sleep mode.
There are 2 16-bit timers(WDT0 and WDT1) and 1 32-bit timer(WDT2) which can be directly used or cascaded.
WDT0 can be cascaded to WDT1, and WDT1 can be configured to generate an interrupt, hence generating an interrupt once an hour to wake-up the device from deep sleep. Since the wake-up period is in hours, power would be minimized.
Note that the cascading option is not available in the PSoC Creator GUI, but can be done in firmware using API CySysWdtSetCascade() (described in cy_lfclk document)
As you said, you can adjust the WDT0/1 periods on the fly to calibrate the ILO using IMO, when the device wakes up. APIs to compensate and trim ILO frequency are also provided in the cy_lfclk document.

The 32-bit WDT2 counter can also be used directly without cascade, but its period can only be in powers of 2. So finer granularity in period may not be possible with the 32-bit WDT2.

Reference Documents:
1) PSoC 4100/4200 Family Architecture TRM ( https://www.cypress.com/file/126171/download )
Watchdog Timer Chapter (page 74-77)
2) PSoC 4 Low-Frequency Clock (cy_lfclk) ( https://www.cypress.com/file/369061/download ) or (PSoC Creator Help -> System Reference Guides)

Best Regards,
Prem Sai

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