# Lower the Sense clock frequency

Level 5
Level 5

Hi.

My customer use PSoC 4100S Plus.

My customer changed Sense clock frequency on the CapSense Tuner.

3000kHz   =>  1500kHz

I recognize that if you lower the Sense clock frequency, the raw count will decrease.

However, this change has increased raw count.

What could be the cause?

Best Regards.

1 Solution

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

How should sense clock frequency be set?

The sense clock frequency should be set such that it charges and discharges the sensor completely (within time).

You can calculate this by using the 5 RC rule. The max Fsw that can be set is governed by the following equation:

FSW(maximum) = 1/ (10RSeriesTotalCp)

Total Series Resistance RSeriesTotal = REXT + RGPIO

CP is the sensor parasitic capacitance, and RSeriesTotal is the total series-resistance, including the 500-ohm resistance of the internal switches, the recommended external series resistance of 560 ohm (connected on PCB trace connecting sensor pad to the device pin), and trace resistance if using highly resistive materials (example ITO or conductive ink); i.e., a total of 1.06 k plus the trace resistance.

The value for CP can be estimated using the CSD Built-in-Self-test API; GetSensorCapacitance().

Why IDAC code/ IDAC gain () changes when Fsw is changed when IDAC auto - calibration is enabled?

Raw count equation for single sinking IDAC - Only mod IDAC, no comp IDAC:

Raw count equation for dual sinking IDAC - Both mod IDAC and comp IDAC:

where Imod = Idac code * IDAC gain. The default calibration percent is fixed by the component to be 85 % of max rawcount (+/- 10 % : accuracy). Therefore, when there is no touch baseline is set at 85 % of max rawcounts (2^ N -1). The role of the IDAC auto - calibration is to find the IDAC codes and IDAC gain (in case of Capsense component v7.0 or higher) based on the other variables such as Fsw, Vref and Cs. Changing any of these parameters will change the IDAC code to bring back the raw counts to 85 % of raw count. That is why changing Fsw changes IDAC code. As long as the rawcount is within +/- 10 % of the max rawcount, increase or decrease in rawcount level (baseline) can not be predicted due to the granularity of the IDAC codes.

All this is valid only if question 1 is satisfied.

Regards,

Regards,
12 Replies

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hello Asanuma san,

Raw count is directly proportional to sense clock frequency. However, there are other parameters also which affect the raw count.

Please check 'Equation 3-6.Single IDAC Sourcing Raw Count' and 'Equation 3-7.Single IDAC Sinking Raw Count' in CapSense Design Guide (https://www.cypress.com/file/46081/download ).

Could you please check whether there is change in any other parameters of the above equation in customer's project, even though they reduced sense clock frequency from 3000kHz to 1500kHz?

Regards,

Kavya

# Re: Lower the Sense clock frequency

Level 5
Level 5

Dear Kavya-san

My customer haven't changed any parameters other than Sense clock frequency on CapSense Tuner.

Is it possible that changing a parameter in CapSense Tuner will change other parameter somewhere?

Also, if the button size is large, Cp will be high. Does this make the raw count more susceptible to changes?

Best Regards,

Asanuma

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

I'm assuming that you have enabled the auto-  calibration in the capsense component window,

Decreasing the sense clock frequency (Fsw), will decrease the IDAC code to maintain the rawcounts at same calibration percent. The auto calibration routine has an accuracy of  +/- 10 %. Hence, if you observe the new raw counts to be +/- 10 % of the 85% rawcounts  then it is expected.

Why does the IDAC change? The answer is when any hardware parameters is changed from tuner (such as resolution, sense clock, IDAC), the Tuner issues a reset command that restarts the capsense component. This will cause the IDAC auto calibration routine to calculate the new IDAC for the new sense clock frequency.

Now, if the auto - calibration routine is disabled, raw count behaves directly proportional to the sense clock frequency. No re calibration occurs and IDAC is not changed. The raw counts decrease if sense clock frequency is reduced.

Set Fsw such that your sensors are charged and discharged completely. (or follow the 10 RC rule) mentioned in the capsense design guide.

Regards,

Regards,

# Re: Lower the Sense clock frequency

Level 5
Level 5

Auto - calibration is disabled.

But, if you lower the Sense Clock, the Raw Count will increase.

Also, does Cp affect this issue?

As the button size increases, Raw Count increases regardless of the finger area.

Best Regards,

Asanuma

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

Could you please let us know the following values used in your project?

a. Mod Clock, Resolution

b. Sense clock (initial setting)

c. Comp IDAC and Mod IDAC set

d. IDAC gain setting in the component

e. Raw count at initial Fsw setting

f. Raw count after changing Fsw value

As the button size increases, the area of contact between the button and the finger increases. This increases the Cf (finger capacitance) and hence increases the signal.

Regards,

Regards,

# Re: Lower the Sense clock frequency

Level 5
Level 5

Since this is customer information, I answer within my understanding.

a. 24000kHz , 12bit

b. 3000kHz

c. IDAC sourcing

d. Enable IDAC auto-  calibration

e. 1050

f. 650 (6000kHz)

This is an example in which Raw Count decreases even if Sense clock frequency is increased.

Best Regards,

Asanuma

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

Have you changed the calibration percent in your firmware? Because when auto calibration is enabled, you should see the baseline at 85% of 2^12 = ~3481? What is the IDAC values you are seeing in the Tuner GUI? If you have not modified the calibration percent, looks like the calibration routine has failed. Could you please make sure Fsw is set such the sensors are charged and discharged completely?

Rawcount equation is valid only if the sensors are charged and discharged completely to Vref.

Regards,

Regards,

# Re: Lower the Sense clock frequency

Level 5
Level 5

I'm sorry, I mistake for "CSD tuning mode".

CSD tuning mode : Manual tuning

IDAC auto-  calibration : Enable

If it is 3000, 6000kH, does it mean that charging and discharging are not in time?

Will IDAC change if I change Fw?

I would like to know how IDAC affects it.

Best Regards,

Asanuma

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

How should sense clock frequency be set?

The sense clock frequency should be set such that it charges and discharges the sensor completely (within time).

You can calculate this by using the 5 RC rule. The max Fsw that can be set is governed by the following equation:

FSW(maximum) = 1/ (10RSeriesTotalCp)

Total Series Resistance RSeriesTotal = REXT + RGPIO

CP is the sensor parasitic capacitance, and RSeriesTotal is the total series-resistance, including the 500-ohm resistance of the internal switches, the recommended external series resistance of 560 ohm (connected on PCB trace connecting sensor pad to the device pin), and trace resistance if using highly resistive materials (example ITO or conductive ink); i.e., a total of 1.06 k plus the trace resistance.

The value for CP can be estimated using the CSD Built-in-Self-test API; GetSensorCapacitance().

Why IDAC code/ IDAC gain () changes when Fsw is changed when IDAC auto - calibration is enabled?

Raw count equation for single sinking IDAC - Only mod IDAC, no comp IDAC:

Raw count equation for dual sinking IDAC - Both mod IDAC and comp IDAC:

where Imod = Idac code * IDAC gain. The default calibration percent is fixed by the component to be 85 % of max rawcount (+/- 10 % : accuracy). Therefore, when there is no touch baseline is set at 85 % of max rawcounts (2^ N -1). The role of the IDAC auto - calibration is to find the IDAC codes and IDAC gain (in case of Capsense component v7.0 or higher) based on the other variables such as Fsw, Vref and Cs. Changing any of these parameters will change the IDAC code to bring back the raw counts to 85 % of raw count. That is why changing Fsw changes IDAC code. As long as the rawcount is within +/- 10 % of the max rawcount, increase or decrease in rawcount level (baseline) can not be predicted due to the granularity of the IDAC codes.

All this is valid only if question 1 is satisfied.

Regards,

Regards,

# Re: Lower the Sense clock frequency

Level 5
Level 5

Is the maximum value of Fsw small when 560Ω is not connected?

Best Regards,

Asanuma

# Re: Lower the Sense clock frequency

Moderator
Moderator

Hi taas_3144281​,

As per equation shared in my previous response, decreasing series resistor increases the maximum Fsw that can be set.

(ie) when Rseries decreases, time constant decreases (= RC), thus Fsw can be increased.

Regards,

Regards,

Level 5
Level 5

Best Regards,

Asanuma