- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Are there any limitations on the processor core when using the emulated EEPROM component. Does the CPU stop while the Flash is being written to for example?
Solved! Go to Solution.
- Labels:
-
PSoC 4 Architecture
- Tags:
- emulated eeprom
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
There are blocking writes and non-blocking writes for em_eeprom component. A side effect can be (device dependent) that the clock frequency might get changed during the write. For details see in System Reference Guide (from Creator help).
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The CPU requires a specific speed when running the flash operations underlying the EEPROM Emulation, and take a noticeable amount of time and current to run. The CPU keeps running, but blocks/polls while operating.
Depending on what kind of chip you have, there is some additional functionality that may change the statement above (the PSoC 6 has more functionality and behavior).
As long as you have enough voltage, and don't mind the CPU bumping to 24MHz (IIRC) when writing flash, then it sounds like the EEPROM emulation writes will run asynchronously to the CPU? (It might block in the API for clarity's sake)
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
There are blocking writes and non-blocking writes for em_eeprom component. A side effect can be (device dependent) that the clock frequency might get changed during the write. For details see in System Reference Guide (from Creator help).
Bob