Is cy8c4 Adc so slow?

[songzaiwu]

Is cy8c4 Adc so slow?

Convert 5 channels, the time is more than 10us。

[DennisS_46 · Accepted solution]

songzaiwu:
your clock is too slow.
Set the clock to 12.0 MHz in the general tab. Set acquisition time to 2 clock cycles (setting lower doesn't work).
That yields 1.33 usec per channel conversion time.

---- Dennis Seguine, PSoC Applications Engineer

[Raj_C]

Hi @songzaiwu,

Adding to @DennisS_46's response, the maximum allowable clock frequency depends on the Vref voltage selection.

Taking PSoC 4100/4200 device Vref voltage selection as an example, the maximum allowable frequency will be as follows:

The displayed Acquisition time in your attached image is equal to (Nclk - 0.5)*(1/Fclk), where Nclk is the number of acquisition ADC clocks, and Fclk is the clock frequency. 

Total acquisition and conversion time (sar_clk) = acquisition time + resolution (bit) + 2

As the Fclk is higher the time taken will be lesser.

Please, let us know if you need further clarification.

Thank you

Best Regards

Raj Chaudhari