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Hi Sir ,
Now I have a project using Casense ,GPIO interrupt ,1ms interrupt ,200us interupt. SW1 ...SW7 are capsense pins. T-TX is GPIO ,strong drive 。R-RX is input
IO with intettupt.
If I set the priority as follows , the board works well.
If I set the priority as follows ,
the T-TX output has a problem , it has a glitch,with a width about 2us.
I have checked for three days . I doubt that when capsense interrupt happens, The GPIO data register has been pushed into stack.
Is that right ? That confuse me .
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Hi,
Can you please attach a demo project that reproduces this issue? We would like to reproduce the issue here and provide you the solution.
Thanks and regards
Ganesh
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Hi Ganesh,
I am sorry the project is in the customer's computer ,so I cann't share it to you . We draw a conclusion that , the interrupt priority must be equal or higher than the other interrupt priority.
Thanks .
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Hi,
I guess the issue you are facing is because of the high priority interrupt present in the code.
To analyze the issue better, please create a demo project that reproduces the same issue and attach here for us to debug.
Thanks
Ganesh