Announcements

Help us improve the Power & Sensing Selection Guide. Share feedback

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
Anonymous
Not applicable

An attempt has been made to implement an Incremental ADC on PSoC4, based on the Topology No. 3 provided by Dave Van Ess in the below article in EE Times:

   

 

   

http://electronicdesign.com/analog/my-favorite-modulator-only-needs-leftover-components

   

 

   

Attached is the PSoC Creator project demonstrating this. Though a 16-bit result is generated, the ADC result is reduced to 12-bit and displayed to reduce noise.

   

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

   

Steps to test this project on a PSoC4 Pioneer Kit (CY8CKIT-042):

   

1) Build this project and program it into the Pioneer kit.

   

2) As shown in the scehmatic, make the following connections to complete the Delta Sigma modulator: (a) Connect an external 100K resistor between P0[7] and P0[4].    (b) Connect a 0.1 nF capacitor between P0[4] and ground.

   

3) Connect an Analog Input to P0[5].

   

4) Connect P4[1](on J3) of PSoC4 to P12[6] of PSoC5LP(J8). This connection is for sending ADC result using PSoC4 UART through PSoC5LP(which acts as USBUART bridge) to PC.

   

5) Connect USBmini cable betwee the Pioneer kit and PC.

   

6) Open a terminal application on PC(such as Hyperterminal/Teraterm etc). In the terminal application, select the port corresponding to the name "KitProg USB-UART". Set Baud Rate = 115200, Data = 8 bit, Parity = None, Stop Bit =1, Flow Control = None.

   

7) Vary the Analog input between 0 - Vdd, and observe the 12-bit result on the terminal application

   

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

   

Though 4 UDBs have been used in this project, it can be reduced to just 1 UDB/TCPWM block if the PWM is replaced using the clock dividers available in PSoC4 and just an 8-bit counter is used(the MSB 8-bits of the counter can be implemented as a firmware byte which is incremented on the 8-bit counter's interrupts).

   

Thanks & Regards,

   

Prem Sai
 

0 Likes
1 Reply
ViDv_264506
Level 5
Level 5
50 sign-ins 25 sign-ins 5 solutions authored

 Hi, 

   

thanks for the publication - very nice and implemented idea.

   

Regards, 

   

Viktor

0 Likes