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Here is the original thread that addresses this issue. I2c Issues
The issue is marked as answered, but there is no answer to the original question:
Are there known issues using P5.0 and P5.1 as allowed by PSOC creator on this module? I am not getting an ACK if these pins are used.
If I assign the pins to P3.4 and P3.5 (allowed for SCB1 sda and scl), I get proper ACK and function.
If someone could help, I would greatly appreciate it. I already have a board layout done using P5.0 and P5.1.
Solved! Go to Solution.
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Hello,
We tested your project with pin set to P5.0 and P5.1 and checked the output on an oscilloscope. Both the pins are working correctly as a digital output pin.
-Sayani.
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This is not a known issue with CYBLE-022001-00.
Can you reproduce this issue on CYBLE-022001-EVAL EZ-BLE™ PRoC™ Evaluation Board?
If yes, using a 'scope do you observe SCL being held low?
Please upload any relevant 'scope traces, hardware schematic PDF and PSoC Creator project for written for CYBLE-022001-EVAL board for everyone to have a look at it.
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Troy,
Thanks for your reply. Here are answers to your questions:
I am using the CYBLE-022001-EVAL board for development.
SCL is not being held low when using P5[1] for SCL signal. See picture
attached:
With no ACK being received, the I2C master issues a STOP and retry.
When SCL is assigned to P3[5] and SDA is assigned to P3[4], SCL clock
stretching and ACK occur:
I am attaching archive of two projects. One that uses I2C Slave and one
that uses EZI2C SCB configurations. Both function the same.
Scott Coleman
949-289-1578 cell
scott642@cox.net
On Wed, Oct 24, 2018 at 2:01 PM Troy Gentry <community-manager@cypress.com>
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Hello,
We tested your project with pin set to P5.0 and P5.1 and checked the output on an oscilloscope. Both the pins are working correctly as a digital output pin.
-Sayani.