Announcements

Equip yourself to optimize PSoc4 MCUs for Evs at the EV Webinar. Click here to register.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 4 Forum Discussions

OmAb_4672891
Level 2
Level 2
10 replies posted 5 replies posted 10 questions asked

Hello

I am attempting to build a system that uses an I2C sensor. it is an RHT sensor. this is the firmware datasheet
https://paramair.de/app/uploads/2018/01/Amphenol-manual-TELAiRE-ChipCap2-T9602.pdf

I am attempting to read the sensor at a distance. Initially, the distance was 1 m and everything is fine. I googled it and found that i can read at a cable distance of 10m if i switch the baudrate from 100 Kbps to 10 Kbps. (i can read 1 meter at 100 Kbps and 10 meters at 10 Kbps). I really really need it to be able to read at a distance of about 7m (24 feet). Is this theoretically possible? because it works! and i do not understand the math behind it.

In addition, when setting the I2C Master componenet baudrate in the topdesign diagram to 10 Kbps, it gives me an alert saying the actual baudrate is 52 Kbps. Is there a way i can force it to 10Kbps to make sure i have a reliable connection at 10m? or is that a sign of a greater problem. A swift answer would be heavily appreciated as i am on a time crunch.

note: I am using PSOC 4100s Plus, CY8C4147AZI-S465

Thank you so much in advance. I really like this community forum.

Omr

0 Likes
1 Solution
NoriakiT_91
Employee
Employee
100 likes received 50 likes received 25 likes received

The I2C specification document is provided by NXP and the document number is UM10204.

GS004827.png

In the specification there is no specification regarding the bus line length, but many timings are specified.

When the bus line becomes longer, the bus line acts as a resistor.  If the bus line is longer ten times, the resistor becomes ten times bigger, and the rising/falling time is also ten times longer.  This is why the maximum clock is lower when the bus line longer.

To reduce the rising/falling time, it will be effective to reduce the bus line resistance.  This requires thick wire.

Please note that the specification document has a recommendation for a long bus line as follows.

GS004828.png

Regards,

Noriaki

View solution in original post

0 Likes
4 Replies
MotooTanaka
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Hi,

I think that we can configure I2C component "Clock from terminal"

001-I2C_config.JPG

Then we can provide certain frequency clock from the top-design.

002-schematic.JPG

I hope this can be a hint.

Note: I have not tried this with hardware by myself.

moto

0 Likes

If using the external clock, you need to watch out the oversampling factor. If set to 16, it should be 160 kHz.

Dear RodolfoG_11-san,

> If using the external clock, you need to watch out the oversampling factor. If set to 16, it should be 160 kHz.

Thank you! I was not paying attention to it. >_<

Best Regards,

5-Aug-2020

Motoo Tanaka

0 Likes
NoriakiT_91
Employee
Employee
100 likes received 50 likes received 25 likes received

The I2C specification document is provided by NXP and the document number is UM10204.

GS004827.png

In the specification there is no specification regarding the bus line length, but many timings are specified.

When the bus line becomes longer, the bus line acts as a resistor.  If the bus line is longer ten times, the resistor becomes ten times bigger, and the rising/falling time is also ten times longer.  This is why the maximum clock is lower when the bus line longer.

To reduce the rising/falling time, it will be effective to reduce the bus line resistance.  This requires thick wire.

Please note that the specification document has a recommendation for a long bus line as follows.

GS004828.png

Regards,

Noriaki

0 Likes