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What I use : CY8CKIT-042-BLE-A
I have been a lot of fun lately while I using PSoC dev kit. But sometimes it got frustrated if ithis kind problem is occured.
My project's input clock is 12MHz, and I want to get PWM freqeuncy which is 108kHz and 50% dutycycle. And I want to increase the frequency by 1. (108 -> 109-> 110 -> 111...)
So I configured input clock, period, compare like picture above. After finish the compiling, and I checked frequency using oscilloscope. But I only got 106kHz freq which is 2kHz less than my desired frequency. I even change to 109kHz frequency, but I only got 107kHz. Same thing happened this time.
why the frequency always 2kHz less than desired value? And how can I fix this problem?
I hope I get the answer.
Best regards.
Solved! Go to Solution.
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bugkiller,
Since you are using the CY8CKIT-042-BLE-A you can use the ECO (24MHz +/- 200 ppm or better) on this kit.
Changing the PWM input clock to 24MHz here is a table of target PWM output frequency and the Period and Compare values needs to achieve the closest to the target frequencies and close to the 50% duty cycle.
Clock src= | 24000000 | Src tolerance = | +/- 200 ppm | |||||
PWM Output | Period Ideal | Period Real | Period Value | PWM Freq Real | Compare Ideal | Compare Real | Compare Value | Duty Cycle Real |
108000 | 222.2222 | 222 | 221 | 108108.1 | 111.1111 | 111 | 110 | 50.000% |
109000 | 220.1835 | 220 | 219 | 109090.9 | 110.0917 | 110 | 109 | 50.000% |
110000 | 218.1818 | 218 | 217 | 110091.7 | 109.0909 | 109 | 108 | 50.000% |
111000 | 216.2162 | 216 | 215 | 111111.1 | 108.1081 | 108 | 107 | 50.000% |
112000 | 214.2857 | 214 | 213 | 112149.5 | 107.1429 | 107 | 106 | 50.000% |
113000 | 212.3894 | 212 | 211 | 113207.5 | 106.1947 | 106 | 105 | 50.000% |
114000 | 210.5263 | 211 | 210 | 113744.1 | 105.2632 | 105 | 104 | 49.763% |
115000 | 208.6957 | 209 | 208 | 114832.5 | 104.3478 | 104 | 103 | 49.761% |
116000 | 206.8966 | 207 | 206 | 115942.0 | 103.4483 | 103 | 102 | 49.758% |
117000 | 205.1282 | 205 | 204 | 117073.2 | 102.5641 | 103 | 102 | 50.244% |
118000 | 203.3898 | 203 | 202 | 118226.6 | 101.6949 | 102 | 101 | 50.246% |
119000 | 201.6807 | 202 | 201 | 118811.9 | 100.8403 | 101 | 100 | 50.000% |
120000 | 200.0000 | 200 | 199 | 120000.0 | 100.0000 | 100 | 99 | 50.000% |
121000 | 198.3471 | 198 | 197 | 121212.1 | 99.1736 | 99 | 98 | 50.000% |
122000 | 196.7213 | 197 | 196 | 121827.4 | 98.3607 | 98 | 97 | 49.746% |
123000 | 195.1220 | 195 | 194 | 123076.9 | 97.5610 | 98 | 97 | 50.256% |
124000 | 193.5484 | 194 | 193 | 123711.3 | 96.7742 | 97 | 96 | 50.000% |
125000 | 192.0000 | 192 | 191 | 125000.0 | 96.0000 | 96 | 95 | 50.000% |
126000 | 190.4762 | 190 | 189 | 126315.8 | 95.2381 | 95 | 94 | 50.000% |
127000 | 188.9764 | 189 | 188 | 126984.1 | 94.4882 | 94 | 93 | 49.735% |
128000 | 187.5000 | 188 | 187 | 127659.6 | 93.7500 | 94 | 93 | 50.000% |
129000 | 186.0465 | 186 | 185 | 129032.3 | 93.0233 | 93 | 92 | 50.000% |
130000 | 184.6154 | 185 | 184 | 129729.7 | 92.3077 | 92 | 91 | 49.730% |
To achieve slightly improved target PWM output frequencies you can use the IMO at 48 MHz +/- 2%
Here's an adjusted table with the new results:
Clock src= | 48000000 | Src tolerance = | +/- 2% | |||||
PWM Output | Period Ideal | Period Real | Period Value | PWM Freq Real | Compare Ideal | Compare Real | Compare Value | Duty Cycle Real |
108000 | 444.4444 | 444 | 443 | 108108.1 | 222.2222 | 222 | 221 | 50.000% |
109000 | 440.3670 | 440 | 439 | 109090.9 | 220.1835 | 220 | 219 | 50.000% |
110000 | 436.3636 | 436 | 435 | 110091.7 | 218.1818 | 218 | 217 | 50.000% |
111000 | 432.4324 | 432 | 431 | 111111.1 | 216.2162 | 216 | 215 | 50.000% |
112000 | 428.5714 | 429 | 428 | 111888.1 | 214.2857 | 214 | 213 | 49.883% |
113000 | 424.7788 | 425 | 424 | 112941.2 | 212.3894 | 212 | 211 | 49.882% |
114000 | 421.0526 | 421 | 420 | 114014.3 | 210.5263 | 211 | 210 | 50.119% |
115000 | 417.3913 | 417 | 416 | 115107.9 | 208.6957 | 209 | 208 | 50.120% |
116000 | 413.7931 | 414 | 413 | 115942.0 | 206.8966 | 207 | 206 | 50.000% |
117000 | 410.2564 | 410 | 409 | 117073.2 | 205.1282 | 205 | 204 | 50.000% |
118000 | 406.7797 | 407 | 406 | 117936.1 | 203.3898 | 203 | 202 | 49.877% |
119000 | 403.3613 | 403 | 402 | 119106.7 | 201.6807 | 202 | 201 | 50.124% |
120000 | 400.0000 | 400 | 399 | 120000.0 | 200.0000 | 200 | 199 | 50.000% |
121000 | 396.6942 | 397 | 396 | 120906.8 | 198.3471 | 198 | 197 | 49.874% |
122000 | 393.4426 | 393 | 392 | 122137.4 | 196.7213 | 197 | 196 | 50.127% |
123000 | 390.2439 | 390 | 389 | 123076.9 | 195.1220 | 195 | 194 | 50.000% |
124000 | 387.0968 | 387 | 386 | 124031.0 | 193.5484 | 194 | 193 | 50.129% |
125000 | 384.0000 | 384 | 383 | 125000.0 | 192.0000 | 192 | 191 | 50.000% |
126000 | 380.9524 | 381 | 380 | 125984.3 | 190.4762 | 190 | 189 | 49.869% |
127000 | 377.9528 | 378 | 377 | 126984.1 | 188.9764 | 189 | 188 | 50.000% |
128000 | 375.0000 | 375 | 374 | 128000.0 | 187.5000 | 188 | 187 | 50.133% |
129000 | 372.0930 | 372 | 371 | 129032.3 | 186.0465 | 186 | 185 | 50.000% |
130000 | 369.2308 | 369 | 368 | 130081.3 | 184.6154 | 185 | 184 | 50.136% |
"Engineering is an Art. The Art of Compromise."
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Hi bugkiller,
Based on your setting of 12MHz clock and period 111, your theoretical PWM frequency is 12MHz/(111+1) = 107.1KHz.
The PWM clock is derived from IMO clock which has a tolerance of +/- 2%. This could also contribute to the difference.
You can use the more accurate ECO clock for HFClk (Clock1 is derived from HFClk).
Regards,
Pong
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bugkiller,
Since you are using the CY8CKIT-042-BLE-A you can use the ECO (24MHz +/- 200 ppm or better) on this kit.
Changing the PWM input clock to 24MHz here is a table of target PWM output frequency and the Period and Compare values needs to achieve the closest to the target frequencies and close to the 50% duty cycle.
Clock src= | 24000000 | Src tolerance = | +/- 200 ppm | |||||
PWM Output | Period Ideal | Period Real | Period Value | PWM Freq Real | Compare Ideal | Compare Real | Compare Value | Duty Cycle Real |
108000 | 222.2222 | 222 | 221 | 108108.1 | 111.1111 | 111 | 110 | 50.000% |
109000 | 220.1835 | 220 | 219 | 109090.9 | 110.0917 | 110 | 109 | 50.000% |
110000 | 218.1818 | 218 | 217 | 110091.7 | 109.0909 | 109 | 108 | 50.000% |
111000 | 216.2162 | 216 | 215 | 111111.1 | 108.1081 | 108 | 107 | 50.000% |
112000 | 214.2857 | 214 | 213 | 112149.5 | 107.1429 | 107 | 106 | 50.000% |
113000 | 212.3894 | 212 | 211 | 113207.5 | 106.1947 | 106 | 105 | 50.000% |
114000 | 210.5263 | 211 | 210 | 113744.1 | 105.2632 | 105 | 104 | 49.763% |
115000 | 208.6957 | 209 | 208 | 114832.5 | 104.3478 | 104 | 103 | 49.761% |
116000 | 206.8966 | 207 | 206 | 115942.0 | 103.4483 | 103 | 102 | 49.758% |
117000 | 205.1282 | 205 | 204 | 117073.2 | 102.5641 | 103 | 102 | 50.244% |
118000 | 203.3898 | 203 | 202 | 118226.6 | 101.6949 | 102 | 101 | 50.246% |
119000 | 201.6807 | 202 | 201 | 118811.9 | 100.8403 | 101 | 100 | 50.000% |
120000 | 200.0000 | 200 | 199 | 120000.0 | 100.0000 | 100 | 99 | 50.000% |
121000 | 198.3471 | 198 | 197 | 121212.1 | 99.1736 | 99 | 98 | 50.000% |
122000 | 196.7213 | 197 | 196 | 121827.4 | 98.3607 | 98 | 97 | 49.746% |
123000 | 195.1220 | 195 | 194 | 123076.9 | 97.5610 | 98 | 97 | 50.256% |
124000 | 193.5484 | 194 | 193 | 123711.3 | 96.7742 | 97 | 96 | 50.000% |
125000 | 192.0000 | 192 | 191 | 125000.0 | 96.0000 | 96 | 95 | 50.000% |
126000 | 190.4762 | 190 | 189 | 126315.8 | 95.2381 | 95 | 94 | 50.000% |
127000 | 188.9764 | 189 | 188 | 126984.1 | 94.4882 | 94 | 93 | 49.735% |
128000 | 187.5000 | 188 | 187 | 127659.6 | 93.7500 | 94 | 93 | 50.000% |
129000 | 186.0465 | 186 | 185 | 129032.3 | 93.0233 | 93 | 92 | 50.000% |
130000 | 184.6154 | 185 | 184 | 129729.7 | 92.3077 | 92 | 91 | 49.730% |
To achieve slightly improved target PWM output frequencies you can use the IMO at 48 MHz +/- 2%
Here's an adjusted table with the new results:
Clock src= | 48000000 | Src tolerance = | +/- 2% | |||||
PWM Output | Period Ideal | Period Real | Period Value | PWM Freq Real | Compare Ideal | Compare Real | Compare Value | Duty Cycle Real |
108000 | 444.4444 | 444 | 443 | 108108.1 | 222.2222 | 222 | 221 | 50.000% |
109000 | 440.3670 | 440 | 439 | 109090.9 | 220.1835 | 220 | 219 | 50.000% |
110000 | 436.3636 | 436 | 435 | 110091.7 | 218.1818 | 218 | 217 | 50.000% |
111000 | 432.4324 | 432 | 431 | 111111.1 | 216.2162 | 216 | 215 | 50.000% |
112000 | 428.5714 | 429 | 428 | 111888.1 | 214.2857 | 214 | 213 | 49.883% |
113000 | 424.7788 | 425 | 424 | 112941.2 | 212.3894 | 212 | 211 | 49.882% |
114000 | 421.0526 | 421 | 420 | 114014.3 | 210.5263 | 211 | 210 | 50.119% |
115000 | 417.3913 | 417 | 416 | 115107.9 | 208.6957 | 209 | 208 | 50.120% |
116000 | 413.7931 | 414 | 413 | 115942.0 | 206.8966 | 207 | 206 | 50.000% |
117000 | 410.2564 | 410 | 409 | 117073.2 | 205.1282 | 205 | 204 | 50.000% |
118000 | 406.7797 | 407 | 406 | 117936.1 | 203.3898 | 203 | 202 | 49.877% |
119000 | 403.3613 | 403 | 402 | 119106.7 | 201.6807 | 202 | 201 | 50.124% |
120000 | 400.0000 | 400 | 399 | 120000.0 | 200.0000 | 200 | 199 | 50.000% |
121000 | 396.6942 | 397 | 396 | 120906.8 | 198.3471 | 198 | 197 | 49.874% |
122000 | 393.4426 | 393 | 392 | 122137.4 | 196.7213 | 197 | 196 | 50.127% |
123000 | 390.2439 | 390 | 389 | 123076.9 | 195.1220 | 195 | 194 | 50.000% |
124000 | 387.0968 | 387 | 386 | 124031.0 | 193.5484 | 194 | 193 | 50.129% |
125000 | 384.0000 | 384 | 383 | 125000.0 | 192.0000 | 192 | 191 | 50.000% |
126000 | 380.9524 | 381 | 380 | 125984.3 | 190.4762 | 190 | 189 | 49.869% |
127000 | 377.9528 | 378 | 377 | 126984.1 | 188.9764 | 189 | 188 | 50.000% |
128000 | 375.0000 | 375 | 374 | 128000.0 | 187.5000 | 188 | 187 | 50.133% |
129000 | 372.0930 | 372 | 371 | 129032.3 | 186.0465 | 186 | 185 | 50.000% |
130000 | 369.2308 | 369 | 368 | 130081.3 | 184.6154 | 185 | 184 | 50.136% |
"Engineering is an Art. The Art of Compromise."
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That is most detatiled answer that I ever get. Thanks guys!
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bugkiller,
At high frequencies, the PWM output has rough granularity, so precise equidistant spacing: 108khz, 109khz, 110khz is not achievable.
To produce precise output frequencies you can use DDS component instead.
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You can crank the IMO up to 48 MHz. You find that the error generally drops with higher IMO.
The plot shows the maximum error over the range of 108 to 130 kHz in absolute Hz.
And, of course you must add in the +/- 2% error from the IMO, unless you use the ECO to achieve better precision
This gets rid of the IMO error, but not the divisor granularity.
Check out the code example as suggested by odissey1
---- Dennis