Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 4

Anonymous
Not applicable

I have a design where I am getting the warning:

Warning: sta.M0021: project_timing.html: Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "CyHFCLK". See the timing report for details.

This warning is not an error in my design, as I know that the data is stable for the time period that I am registering it.  I'd like to have permanently ignore this warning, so it doesn't show up on every build.

Is there a timing constraints file (like those found in FPGA tools) or other method that I can have the tools ignore this path?

Brian

0 Likes
1 Solution
Bob_Marlowe
Level 10
50 questions asked 10 questions asked 1000 solutions authored
Level 10

I would suggest to add a ClockSync component.

Bob

View solution in original post

0 Likes
2 Replies