I have a design where I am getting the warning:
Warning: sta.M0021: project_timing.html: Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "CyHFCLK". See the timing report for details.
This warning is not an error in my design, as I know that the data is stable for the time period that I am registering it. I'd like to have permanently ignore this warning, so it doesn't show up on every build.
Is there a timing constraints file (like those found in FPGA tools) or other method that I can have the tools ignore this path?
Brian
