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PSoC™ 4 Forum Discussions

Anonymous
Not applicable

I have a design where I am getting the warning:

Warning: sta.M0021: project_timing.html: Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "CyHFCLK". See the timing report for details.

This warning is not an error in my design, as I know that the data is stable for the time period that I am registering it.  I'd like to have permanently ignore this warning, so it doesn't show up on every build.

Is there a timing constraints file (like those found in FPGA tools) or other method that I can have the tools ignore this path?

Brian

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1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

I would suggest to add a ClockSync component.

Bob

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2 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

I would suggest to add a ClockSync component.

Bob

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Roy_Liu
Moderator
Moderator
Moderator
1000 replies posted 500 solutions authored 5 questions asked

The following apps note may be helpful.

AN81623 - PSoC® 3, PSoC 4, and PSoC 5LP Digital Design Best Practices

Roy Liu
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