Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
chwa_1570756
Level 4
Level 4
25 sign-ins 25 replies posted 10 replies posted

Hello,

I made a 4-bit count component by verilog HDL, how can I set up a API like those standard components? such as the command of  Counter_WriteCounter(), Counter_ReadCounter().

Chris

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Attached is a demo project showing instantiation of the Control and Status registers inside the custom BCounter component. The basic PLD Verilog can only communicate with API through those registers.

In this demo the custom component output  bus is connected to the myStatusReg in transparent mode and can be read using ReadCnt() API.

Setting the counter value is done through the myControlReg. The counter value can be loaded from this register on the external 'load' signal.

 

Figure 1. Project schematic. The new counter value is loaded on the tc pulse. The external status register Sreg_1 is optional; it is added to compare with ReadCnt() API results. 

CounterEx_01a_A.png

Figure 2. Putty terminal output showing the Counter value after each clock. The counter starts with 0, but once it rolls over, the tc signal reloads counter value  (cnt=7) again. 

CounterEx_01a_Putty.png

 

Figure 3. Project annotation using KIT-044 annotation library. No external connections are needed.

SerialRx_P4_SCB_01a_KIT-044b.png  

View solution in original post

5 Replies
RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Chris,

check application notes AN82156 & AN82250, those cover component creation including API and they come with example files.

Regards

0 Likes
lock attach
Attachments are accessible only for community members.
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Attached is a demo project showing instantiation of the Control and Status registers inside the custom BCounter component. The basic PLD Verilog can only communicate with API through those registers.

In this demo the custom component output  bus is connected to the myStatusReg in transparent mode and can be read using ReadCnt() API.

Setting the counter value is done through the myControlReg. The counter value can be loaded from this register on the external 'load' signal.

 

Figure 1. Project schematic. The new counter value is loaded on the tc pulse. The external status register Sreg_1 is optional; it is added to compare with ReadCnt() API results. 

CounterEx_01a_A.png

Figure 2. Putty terminal output showing the Counter value after each clock. The counter starts with 0, but once it rolls over, the tc signal reloads counter value  (cnt=7) again. 

CounterEx_01a_Putty.png

 

Figure 3. Project annotation using KIT-044 annotation library. No external connections are needed.

SerialRx_P4_SCB_01a_KIT-044b.png  

Hi odissey1,

This demo project make many things clear, thanks!

Chris

0 Likes
lock attach
Attachments are accessible only for community members.

Attached are pretty much all of the PSoC - related Verilog resources which may be helpful.

0 Likes

Hi odissey1,

Some of documents are really helpful, thanks.

Chris

0 Likes