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PSoC™ 4 Forum Discussions

HaLi_1053816
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I have tried it, seem as 3MHZ, is it correct? Thanks.

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The DMA channel is triggered by a logic HIGH/1 on the tr_in terminal. The minimum width of this logic HIGH/1 is 2 system clock (SYSCLK) cycles.

Thanks,

Ryan

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RyanZhao
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Dear Mr.Liu,

If the uA or bits value in the Component configuration GUI is set a fixed value, IDAC will keep a stable output.

What do you mean " data update ratio"?

Do you mean if you use Some APIs, like 'IDAC7_SetValue()', to update the output of IDAC7 in run time?

Thanks,

Ryan

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HaLi_1053816
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Hello Ryan,

I use DMA drive the IDAC, my mean's DMA transfer data ratio.

Thank a lot.

Haixian

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The DMA channel is triggered by a logic HIGH/1 on the tr_in terminal. The minimum width of this logic HIGH/1 is 2 system clock (SYSCLK) cycles.

Thanks,

Ryan

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