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PSoC™ 4 Forum Discussions

chva_349096
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Hi,

   

I am trying to use the UART (UDB based) in Half-Duplex mode.  I am finding that it will not compile with the following error:

   

Error: plm.M0046: E2071: Unable to pack the design into 4 UDBs. See the Digital Placement section of the report file for details. For additional assistance, see the Mapper, Placer, Router section in the PSoC Creator help.
Error: plm.M0046: E2055: An error occurred during placement of the design.

   

If I change that UART to Full, it compiles without a problem.

   

I am unable to use the SCB UART and the Full UART does not leave enough resources for my other components.

   

Attached is a project which demonstrates this issue on the CYBLE-014008-00 PSOC 4.  It only has a single UART component and main.c does nothing.

   

Thoughts?

   

- Chris

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1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Use full duplex, that will compile.

   

 

   

Bob

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3 Replies
chva_349096
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Sometimes it helps to click on the magnifying glass.  I am not sure if this solution is going to work, but I will try it and report back.  It seems odd that this component would not work out of the box.

   

The placer is not able to place all of the carry chains without backtracking. It fills one UDB bank to 15/16 and the other to 7/8 and cannot place the final 2-datapath chain. As a workaround, add a control file to the TopDesign component (in Workspace Explorer's Components tab) with the following lines: ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)"; This will fill the datapaths in the second UDB bank and allow the placer to assign the remaining datapaths.

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chva_349096
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Creating the component file with these lines:

   

ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; 
ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; 
ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)";

   

Does not appear to resolve or change the problem.  It is possible I am not creating it properly.  I created a "TopDesign.ctl" file with those three lines and it appears on the Components Tab, under the TopDesign component.

   

Any ideas would be appreciated.  Thanks.

   

- Chris

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Use full duplex, that will compile.

   

 

   

Bob

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