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fewa_4357111
Level 1
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Distributor - Zenitron(GC)
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Dear All,

     In the test process, there is a certain probability of the following errors: when the host sends a read command to P4, SDA is pulled down, ezi2c replies to Nck, and the data read by subsequent hosts are all wrong.

WeChat 截圖_20201029144208.pngWeChat 截圖_20201029144235.png

Best Regards,

Ferris

Make you stronger
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1 Solution

从你们提供的波形看,这个IIC Master 产生的 CLK/SDA 波形应该是一个软件模拟的,不像是纯硬件的。我的建议是你们最好找到可以容易问题的方法,然后使用好一些的逻辑分析仪(可以同时抓模拟通道)来解析一下问题出现时 SCL 上是否出现了窄脉冲 glitch, 从而导致 clock 错位。这种 glitch 比较窄的话,使用示波器和逻辑分析仪数字通道是很难抓取到的,但是逻辑分析仪的模拟通道一般都可以抓取到。

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6 Replies
Vison_Zhang
Moderator
Moderator
Moderator
First comment on KBA 750 replies posted 250 sign-ins

1. Replace the I2C Master with BCP+Miniprog3/Miniprog4/KitProgx, see if this issue is reproducible or not. 

2. Let's assume there has a glitch pulse during I2C Master send slave address out and this glitch is treated as a normal clock pulse by I2C slave, then is the data read out from i2c slave correct?

Capture.PNG

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Sophie_Wang
Level 4
Level 4
Distributor - Zenitron(GC)
25 replies posted 10 replies posted 5 replies posted

Hi Vison,

谢谢。现在可以确认的是,用BCP+miniprog3复现不出来。

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从你们提供的波形看,这个IIC Master 产生的 CLK/SDA 波形应该是一个软件模拟的,不像是纯硬件的。我的建议是你们最好找到可以容易问题的方法,然后使用好一些的逻辑分析仪(可以同时抓模拟通道)来解析一下问题出现时 SCL 上是否出现了窄脉冲 glitch, 从而导致 clock 错位。这种 glitch 比较窄的话,使用示波器和逻辑分析仪数字通道是很难抓取到的,但是逻辑分析仪的模拟通道一般都可以抓取到。

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Sophie_Wang
Level 4
Level 4
Distributor - Zenitron(GC)
25 replies posted 10 replies posted 5 replies posted

Hi Vison,

谢谢。

客户定义的buffer是12bytes, 如果在您划出的地方多出一个波形,那客户读寄存器的位置就从00变成了80。

Scb datasheet上似乎说I2C Master不能读到定义buffer以外位置的数据。

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我只是举个例子,如果读到的异常数据和正常数据之间存在明显的相关性(比如移位,ACK/NACK 位被识别成数据位等),那么就可以反过来验证我们的推理是正确的。

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Sophie_Wang
Level 4
Level 4
Distributor - Zenitron(GC)
25 replies posted 10 replies posted 5 replies posted

好的,谢谢支持。

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