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PSoC™ 4 Forum Discussions

KaKi_1384211
Level 6
Level 6
100 replies posted 50 replies posted 50 questions asked

Hi Team,

Please let me know about the following PCB layout design regarding capsense for PSoC4200.

For series resistance of capsense pins, in the design guide, It is arranged within 10mm of the PSoC pin, and individual chip resistors are used.

Now, we are considering this resistance with the resistor array(Panasonic EXB28V, etc.).

At that time, it is assumed that the parasitic capacitance between the wiring patterns affects by using a resistor array.

Please let me know the design rules on capsense wiring patterns and the recommendations, prohibitions and design materials for making resistor array from series resistance.

Thanks and regards,

1 Solution
RyanZhao
Moderator
Moderator
Moderator
750 replies posted 100 sign-ins 100 likes received

Kikuma-san,

I haven't tried using resistance array before. But in my mind, resistance array may increase sensors' coupling noise. For example, if you touch on one sensor, others sensors may become ON due to noise couple.

In capsense design, ideally, sensor traces require to be separated with each other. Recommend to use GND(or reserve enough clearance) to separate sensors' trace one by one.

Thanks,

Ryan

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1 Reply
RyanZhao
Moderator
Moderator
Moderator
750 replies posted 100 sign-ins 100 likes received

Kikuma-san,

I haven't tried using resistance array before. But in my mind, resistance array may increase sensors' coupling noise. For example, if you touch on one sensor, others sensors may become ON due to noise couple.

In capsense design, ideally, sensor traces require to be separated with each other. Recommend to use GND(or reserve enough clearance) to separate sensors' trace one by one.

Thanks,

Ryan

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