Creating Audio with DMA

[jofic_334026]

I'm using the IDAC component to generate a 3kHz beeping tone.  It beeps at a 50% duty cycle.  My solution must be all in hardware.  I'm using a DMA to transfer values to the IDAC.  If I allow the DMA to run continuously a clean 3kHz tone is generated.  I want it to beep so I use the "BeepTimer" to turn ON/OFF the signal to the "tr_in" pin of the DMA component.  I'm trying to reduce the "popping" of the speaker when the "BeepTimer" turns off the signal to the "tr_in" pin.  To do that, theoretically, I should wait until the end of the DMA transfer before turning the speaker off.  That's because at the very end of the DMA transfer the tone is always at a 0 point.

In the attached project I connected the output of the "BeepTimer" to a D flip-flop that gets clocked by the "tr_out" signal of the DMA.  This should (theoretically) delay the "BeepTimer" output until the end of a DMA transfer.  However, for some reason, this is not working.  I get an Asynchronous path warning but I don't think that's the problem.  Why is this D flip-flop arrangement not working?

[odissey1 · Accepted solution]

user_46..,

Attached is a screenshot of the Beeper demo, where wave shut-off occurs exactly at the end of DMA transaction. Project is not included as it was drafted in PSoC5 (WaveGen8 is 8-bit DMA bridge, but PSoC4 needs 16-bit), but the essential part is SR flip-flop and associated logic in the lower left corner. Here the DMA clock is enabled on SRFF "set" signal (clock_3 is high) and it will reset only after clock_3 is low and wave transfer is complete (notice that wave continues almost 1/4 of the period after the control signal is off).

If IDAC has h/w enable pin, it can be used to turn output on/off using same schematic (while DMA continuously transfers the data to IDAC).

/odissey1