Create Monostable

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AuKa_4634111
Level 2
Level 2
5 replies posted First like received First reply posted

I am trying to create a Monostable of 300mS than is triggered every second. It was easy enough when I worked with a 16 bit counter because a PWM counter (ms_Counter) with a period of 10000 (with a clock of 10KHz) and a Compare setting of 3000 was the perfect solution. Unfortunately  I needed greater resolution for  the period and since the component can only be configured for 16 bits, I went to a 24bit counter with a clock of 1MHz and a Period of 1000000 (OneSecCounter)which generated 1 Hz.  I tried to get it to trigger (using the reload pin) a PWM counter with a period of 65000 and the Compare remained at 3000. I tried to get the TC of the 24 bit counter to reload the PWM counter as you can see in the attached drawing, but the monostable pulse occurred at a far longer period, perhaps the 65000 which would suggest that the reload does not work the way I think. I also tried the period at 4000 and the output was much faster than the desired 1 second.

According to the datasheet "For all devices, except PSoC 4000, PSoC 4100, PSoC 4200, it should only be used when the counter is not running.", so it seems that I can activate the Reload when it is running. I found the following in the data sheet a little confusing "In up and up/down counting modes, the counter is initialized with “0” (for PSoC 4000, PSoC 4100, PSoC 4200 devices).". Does that mean the reload should be active low? I tried both ways but it made no difference .

In the schematic you can see a divide by 2 D-FF to prove that the OneSecCounter is working. I also include the register settingsScreenshot 2021-11-29 145312.jpgScreenshot 2021-11-29 150013.jpg

Does anyone have any idea what I can do generate the monostable pulse? Any help would be much appreciated!

 

 

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That one is not so obvious, but once you read the reason, you'll say, doh!

(I'm assuming you meant the RELOAD input, not the RESET input).
The RELOAD input is sampled with its own counter CLOCK input (10kHz) at the CLOCK rising edge.
The TC from the 1 second counter is driven by a 1MHz clock.  Therefore, TC is active for just 1 clock cycle at 1MHz.  The probability that TC is active just as a rising edge of 10kHz occurs, is pretty slim.  Hence, the 300ms counter never gets reloaded.

Also, I just noticed there's an inverter in front of the RELOAD input.  This would make the 300ms counter reload continuously.  So, lose the invertor and my explanation holds up.

I hope that was clear enough to understand.  If not, I can try again.

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