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PSoC™ 4 Forum Discussions

Anonymous
Not applicable

 Hi,

   

I found that the SWD pins of PSoC 4 cannot be configured as GPIO though this option is present. To configure a SWD pin to function as GPIO we should write zero to the respective nibble of the register port 3 HSIOM register of PSoC 4. HSIOM register is a 32 bit register and there is one HSIOM register corresponding to each port . HSIOM_PORT_SEL3 corresponds to port 3. Each port has a maximum of 8 pins and each pin can have a maximum of 16 configurations. Hence 4 bits(1 nibble)from HSIOM register is required for each pin of a port. Therefore 32 bits of the register can configure 8 pins  of the port. For detailed information kindly go through HSIOM register of PSoC 4 registers TRM.

   

Thanks,

   

Thinkle

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3 Replies
Anonymous
Not applicable

Good advise!

   

But I don't understand. In my example the pin is configured such, that it's driven from a clock.

   

There is a corresponding bit responsible EXT_CLK 0x08. However this bit is only for Pin6 port0

   

But I have port0 pin4 where such bit don't exists. I've compiled the projects and it's working.

   

But HSIOM for this pin is 0x0, mean standard configuration.

   

Thanks for hint.

   

Seb

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HeLi_263931
Level 8
Level 8
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According to the TRM, port 4 is missing the logic for clocked / synced IOs. So you can only connected unsynchronized IO pins there.

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Anonymous
Not applicable

I very happy with that news, because I'm usung port0

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