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PSoC™ 4 Forum Discussions

YoIs_1298666
Level 5
Level 5
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Hello,

The modulator clock frequency is set to 24000kHz and the sense clock frequency is set to 1500kHz on CSD.

Looking at the "Clocks" tab of "DWR", the clock frequency(Nominal Frequency) of CapSense_ModClk is 94.118kHz.

YoIs_1298666_0-1633485906774.png

What is this clock?

Best regards,

Yocchi

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Ekta
Moderator
Moderator
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250 solutions authored 100 likes received 250 sign-ins

Hi @YoIs_1298666 

Any Local clock that you observe under the clocks Tab of the design wide resources is clock added to schematics via Component. The CapSense_Modclock that you observe here is the clock utilized by the Capsense component internally.

If you want to observe this you can import the capsense component in your design (follow the steps in: https://www.cypress.com/video-library/PSoC-Software/psoc-creator-tutorial-importing-components/10775... to import component). Go to the Components tab in the workspace explorer and observe the schematic. You will notice that there is a Modclock which has a frequency of HFCLK/255 =94.11Khz being utilized in the schematic.

I hope this clears your confusion.

Best Regards
Ekta


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Ekta
Moderator
Moderator
Moderator
250 solutions authored 100 likes received 250 sign-ins

Hi @YoIs_1298666 

Any Local clock that you observe under the clocks Tab of the design wide resources is clock added to schematics via Component. The CapSense_Modclock that you observe here is the clock utilized by the Capsense component internally.

If you want to observe this you can import the capsense component in your design (follow the steps in: https://www.cypress.com/video-library/PSoC-Software/psoc-creator-tutorial-importing-components/10775... to import component). Go to the Components tab in the workspace explorer and observe the schematic. You will notice that there is a Modclock which has a frequency of HFCLK/255 =94.11Khz being utilized in the schematic.

I hope this clears your confusion.

Best Regards
Ekta


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Hello Ekta-san,

Thank you very much for your reply.

I was able to confirm it.

YoIs_1298666_0-1633570488552.png

It's an internal clock that isn't open to users, right?

Best regards,

Yocchi

 

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Ekta
Moderator
Moderator
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250 solutions authored 100 likes received 250 sign-ins

Hi Yocchi-San,

Yes, it's an internal clock utilized by the component.

Best Regards
Ekta

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Hello Ekita-san,

Thank you for your support.

Please tell me one more point.

Can 94.118kHz ModClk of PSoC4000S series directly change the register values to 47.059kHz, which is the same as both ModClk and SnsClk of PSoC4000 series?

Best regards,

Yocchi

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Ekta
Moderator
Moderator
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250 solutions authored 100 likes received 250 sign-ins

Hi Yocchi,

When changing the device from 4000S to 4000 the Modclk frequency should change to 47.059kHz automatically. This is because in the case of 4000 devices by default the HFCLK = IMO(24 Mhz) / 2 = 12 Mhz. 

As mentioned in the previous posts in the schematic for the capsense component odclock which has a frequency of HFCLK/255 = 12Mhz/255 = 47.059kHz.

Kindly let me know if tihs is what you were asking.

Best Regards
Ekta


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Hello Ekta-san,

Thank you very much.

CapSense_ModClk is fixed to HFCLK / 255, right?

Best regards,

Yocchi

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Ekta
Moderator
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250 solutions authored 100 likes received 250 sign-ins

Hi Yocchi,

Yes capsense Modclock is fixed to HFCLK/255.

Best Regards
Ekta

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Hello Ekta-san,

Thank you very much.

Best regards,

Ishii

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