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Hi,
I refer to the I2S code example in the HAL document. I've also attached the code I use.
Log as below:
====
****************** I2S Sample******************
i2s init fail result = 4020b03
====
Please tell us how to work with i2s properly
Solved! Go to Solution.
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Clock init is required to get the correct frequency for running the I2S clock.
By default the I2S Clock is sourced from CLK_HF[1]. One must ensure this frequency is a multiple of 2*sampling rate*channel length*8 (internal divider)
The HF_CLK[1] in turn comes from PLL configured at a multiple of the above-obtained frequency. I have defined the clock_init function in order to ensure that this is followed.
You can refer to the clocking features of the I2S chapter in the PSoC 4 Architecture TRM to better understand the clock requirements
Best Regards
Ekta
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Please refer to the following I2S code that I have functionally tested at my end for the CY8CKIT-041S-MAX.
Note the code was created using MTB 2.4
Thanks and Regards
Ekta
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Hi Ekta,
Thank you for your sample code.
I used MTB3.0, I could compile the code you provide successfully, but can not see the i2s signal by using logical analyzer. I use MTB3.0 Debug mode, then found there was a ASSERT on Cy_SysClk_PeriphDividerIsEnabled(), I'm not sure whether the Assert was related to the problem. Just share my observation.
Please help me with running the I2S sample successfully.
Thank you
Best Regards
Edward
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Hi Ekta,
I marked the clock_init(), it's working on MTB3.0. I can see the i2s signal. My question is why we need the clock_init() function before cyhal_i2s_init()? How to modify the clock_init().
Thank you!
BRs
Edward
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Clock init is required to get the correct frequency for running the I2S clock.
By default the I2S Clock is sourced from CLK_HF[1]. One must ensure this frequency is a multiple of 2*sampling rate*channel length*8 (internal divider)
The HF_CLK[1] in turn comes from PLL configured at a multiple of the above-obtained frequency. I have defined the clock_init function in order to ensure that this is followed.
You can refer to the clocking features of the I2S chapter in the PSoC 4 Architecture TRM to better understand the clock requirements
Best Regards
Ekta