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PSoC™ 4 Forum Discussions

KaKo_4074056
Level 4
Level 4
50 sign-ins 25 sign-ins 10 replies posted

Hello,

Let me confirm the difference between the TRM initialization procedure of SCB (UART and SPI) and the automatically generated code from PSoC Creator.

- PSoC 4100/4200 Family PSoC 4 Architecture TRM (Doc No: 001-85634 Rev. *H)

- SCB Component v4.0

What are the possible negative consequences of not clearing and freezing the FIFO? My customer is concerned.

The TRM explains as follows.

=================================

15.3.6 Enabling and Initializing UART

The UART must be programmed in the following order:

3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-11.

a. Set the trigger level.

b. Clear the transmitter and receiver FIFO and Shift registers.

c. Freeze the TX and RX FIFOs.

=================================

15.2.6 Enabling and Initializing SPI

The SPI must be programmed in the following order:

3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-5:

a. Set the trigger level.

b. Clear the transmitter and receiver FIFO and Shift registers.

c. Freeze the TX and RX FIFO.

=================================

The SCB_Init() API calls SCB_UartInit() and SCB_SPIInit(). In the following, step 3a is processed, but it seems that step 3b and 3c are not processed.

SCB_UartInit() {

        ....

        SCB_RX_FIFO_CTRL_REG = SCB_UART_DEFAULT_RX_FIFO_CTRL;

        SCB_TX_FIFO_CTRL_REG = SCB_UART_DEFAULT_TX_FIFO_CTRL;

        ....

}

SCB_SPIInit() {

        ....

        SCB_RX_FIFO_CTRL_REG = SCB_SPI_DEFAULT_RX_FIFO_CTRL;

        SCB_TX_FIFO_CTRL_REG = SCB_SPI_DEFAULT_TX_FIFO_CTRL;

        ....

}

Thanks.

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1 Solution

Firstly, these are not processing steps but options as initialized setting for UART/SPI actually.

Please take a look at Table 15-11 in TRM(Doc No: 001-85634 Rev. *H)

thread_pic.png

Also I confirmed about “clearing FIFO” in initialization.

> should they be processed when the UART/SPI is reinitialized?

They should be processed. And TX/RX FIFO is cleared at the beginning of UART_UartInit(void) by set the SCB disabled before other initializations.

As Arch TRM described in SCBx_CTRL(Bit 31):

"...Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content) ..."

> I don't think these initializations are necessary immediately after starting the MCU,

After starting the MCU, it’s necessary to set one of these three(a-c), but RX/TX FIFO with any setting(a-c) is also cleared during initialization as default (unless there are some noise or TX/RX line).

This clear operation has been integrated in UART_UartInit(void).

Also In runtime, if SCB UART Stopped and Re-started in run time, it is better to initialize(clear) RX/TX FIFO again.

Because if they are not cleared, it may cause some dirty data on UART TX/RX, caused by the old FIFO data.

Aiko Ohtaka
Infineon Technologies

View solution in original post

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3 Replies
AikoO_51
Moderator
Moderator
Moderator
100 sign-ins First question asked 50 solutions authored

It’s set the transmitter and receiver FIFOs to the trigger level with SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers as default when it’s initialized.

I confirmed it in a definition of UART_Start() API.

If you want to set them to others, you need to do something additionally.

Also how do you confirm that it’s operating as trigger level?

That's already set in initialization API.

Aiko Ohtaka
Infineon Technologies
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Hello,

Sorry for the late reply. Let me confirm again.

Thank you for checking the UART_Start(). In this API, when initializing RIGGER_LEVEL (bit2:0) in TX/RX_FIFO_CTRL register, it seems that "0" is written to bit17:16 respectively. I understand that clearing and freezing are effective by writing "1" to CLEAR (bit16) and FREEZE (bit17). Isn't this necessary as a step in 3b and 3c in TRM?

I don't think these initializations are necessary immediately after starting the MCU, but should they be processed when the UART/SPI is reinitialized?

Best regards,

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Firstly, these are not processing steps but options as initialized setting for UART/SPI actually.

Please take a look at Table 15-11 in TRM(Doc No: 001-85634 Rev. *H)

thread_pic.png

Also I confirmed about “clearing FIFO” in initialization.

> should they be processed when the UART/SPI is reinitialized?

They should be processed. And TX/RX FIFO is cleared at the beginning of UART_UartInit(void) by set the SCB disabled before other initializations.

As Arch TRM described in SCBx_CTRL(Bit 31):

"...Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content) ..."

> I don't think these initializations are necessary immediately after starting the MCU,

After starting the MCU, it’s necessary to set one of these three(a-c), but RX/TX FIFO with any setting(a-c) is also cleared during initialization as default (unless there are some noise or TX/RX line).

This clear operation has been integrated in UART_UartInit(void).

Also In runtime, if SCB UART Stopped and Re-started in run time, it is better to initialize(clear) RX/TX FIFO again.

Because if they are not cleared, it may cause some dirty data on UART TX/RX, caused by the old FIFO data.

Aiko Ohtaka
Infineon Technologies
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