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DeanG
Level 3
Level 3
10 replies posted First like given 5 questions asked

Working with a PSOC4 dev board (CY8KIT-149), trying to get SHA256 and CRC crypto functions working.  Both functions constantly return 0.  Cy_Crypto_Enable(CRYPTO) is successful, all of the other functions return success, but the SHA256 is zero, which isn't correct.   Here's the snippet of code I'm using:

void update(uint8_t *hash)
{
    cy_en_crypto_status_t cy_status;

    uint32_t *app_flash = (uint32_t*)CY_DFU_APP1_VERIFY_START;
    CY_ALIGN(4) uint32_t buffer[CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)] = {0};
    CY_ALIGN(4) uint8_t image_hash[CY_CRYPTO_SHA256_DIGEST_SIZE];
    uint32_t flash_offset;



    /// init sha256 object
    cy_status = Cy_Crypto_Sha_Init(CRYPTO,
                                   CY_CRYPTO_MODE_SHA256,  /* Hash mode */
                                   &ctx);

    if (cy_status != CY_CRYPTO_SUCCESS)
    {
        GK_LOG_ERROR("SHA init failed, status: %lu", cy_status);
        return GK_STATUS_CRYPTO_FAILED;
    }


    // Start at beginning of app flash area calc sha256 hash
    flash_offset = CY_DFU_APP1_VERIFY_START;
    while (flash_offset < _curr_offset)
    {
        // read in a row of data
        for(uint32_t i = 0; i < (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)); i++)
        {
           buffer[i] = *app_flash;
           app_flash++;
        }

        flash_offset += CY_FLASH_SIZEOF_ROW;

        // hash chunk
        cy_status = Cy_Crypto_Sha_Partial(CRYPTO, (uint8_t const *)buffer, sizeof(buffer), &ctx);

        if (cy_status != CY_CRYPTO_SUCCESS)
        {
           GK_LOG_ERROR("Failed to hash update, status: %lu", cy_status);
           return GK_STATUS_CRYPTO_FAILED;
        }
    }

	=============> Always returns zero ================
    cy_status = Cy_Crypto_Sha_Finish(CRYPTO, image_hash, &ctx);
    if (cy_status != CY_CRYPTO_SUCCESS)
    {
        GK_LOG_ERROR("Failed to finish hash, status: %lu", cy_status);
        return GK_STATUS_CRYPTO_FAILED;
    }

    cy_status = Cy_Crypto_Sha_Free(CRYPTO, &ctx);

    return GK_STATUS_SUCCESS;
}
 
Just weird,  Cy_Crypto_Sha_Finish() always returns zero.
Same thing when I execute:  cy_status = Cy_Crypto_Crc_Calc(CRYPTO, &crc_32, data, (uint32_t)len, &crc_ctx);
The crc (`crc_32`) is always zero.
 
Besides calling Cy_Crypto_Enable(), is there any other config settings I should be setting?
 
Thanks,
Dean
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JJack
Level 5
Level 5
Associated Partner - Distributor Rutronik
5 questions asked 25 likes received 100 sign-ins

Hi Dean,

I have a CY8CKIT-149 on my desk. It is populated with a PSoC 4100S PLUS = C8C4147AZI-S475.

The include cy_crypto.h file of the PDL says:

"* The Crypto driver provides a public API to perform cryptographic and hash
* operations, as well as generate both true and pseudo random numbers.
*
* It uses a hardware IP block to accelerate operations.
*
* The functions and other declarations used in this driver are in cy_crypto.h.
* You can also include cy_pdl.h to get access to all functions and declarations
* in the PDL."

However, when searching the pdf data sheet of PSoC 4100S PLUS the only find for "crypto" is the HW of the TRNG.

The datasheet also does not show a salestype option "crypto", "HSM" or similar in chapter 5, Ordering Information.

My conclusion therefore is that PSoC 4100S PLUS does not feature the necessary crypto HW IP on the chip for the above mentioned SW-drivers...

Addendum:

Just checked a marketing slide from Infineon, snippet inserted here:

JJack_0-1694503261530.png

-> Migrate to a board with PSoC 4100S Max.

One option for a board with PSoC 4100S Max is the RDK4 from my employer. It is available in the webshop of Rutronik24. Please find manual attached.

BR

JJack

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2 Replies
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JJack
Level 5
Level 5
Associated Partner - Distributor Rutronik
5 questions asked 25 likes received 100 sign-ins

Hi Dean,

I have a CY8CKIT-149 on my desk. It is populated with a PSoC 4100S PLUS = C8C4147AZI-S475.

The include cy_crypto.h file of the PDL says:

"* The Crypto driver provides a public API to perform cryptographic and hash
* operations, as well as generate both true and pseudo random numbers.
*
* It uses a hardware IP block to accelerate operations.
*
* The functions and other declarations used in this driver are in cy_crypto.h.
* You can also include cy_pdl.h to get access to all functions and declarations
* in the PDL."

However, when searching the pdf data sheet of PSoC 4100S PLUS the only find for "crypto" is the HW of the TRNG.

The datasheet also does not show a salestype option "crypto", "HSM" or similar in chapter 5, Ordering Information.

My conclusion therefore is that PSoC 4100S PLUS does not feature the necessary crypto HW IP on the chip for the above mentioned SW-drivers...

Addendum:

Just checked a marketing slide from Infineon, snippet inserted here:

JJack_0-1694503261530.png

-> Migrate to a board with PSoC 4100S Max.

One option for a board with PSoC 4100S Max is the RDK4 from my employer. It is available in the webshop of Rutronik24. Please find manual attached.

BR

JJack

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DeanG
Level 3
Level 3
10 replies posted First like given 5 questions asked

Ahh, @JJack  You are correct.  I was looking at the PSoC 4100S MAX data sheet -- not the PSoC 4100S PLUS.  Many thanks for the clarification.  

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